drivers/clocksource/mps2-timer.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 ARM Limited
0004  *
0005  * Author: Vladimir Murzin <vladimir.murzin@arm.com>
0006  */
0007
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009
0010 #include <linux/clk.h>
0011 #include <linux/clockchips.h>
0012 #include <linux/clocksource.h>
0013 #include <linux/err.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/irq.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/sched_clock.h>
0021 #include <linux/slab.h>
0022
0023 #define TIMER_CTRL      0x0
0024 #define TIMER_CTRL_ENABLE   BIT(0)
0025 #define TIMER_CTRL_IE       BIT(3)
0026
0027 #define TIMER_VALUE     0x4
0028 #define TIMER_RELOAD        0x8
0029 #define TIMER_INT       0xc
0030
0031 struct clockevent_mps2 {
0032     void __iomem *reg;
0033     u32 clock_count_per_tick;
0034     struct clock_event_device clkevt;
0035 };
0036
0037 static void __iomem *sched_clock_base;
0038
0039 static u64 notrace mps2_sched_read(void)
0040 {
0041     return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
0042 }
0043
0044 static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c)
0045 {
0046     return container_of(c, struct clockevent_mps2, clkevt);
0047 }
0048
0049 static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset)
0050 {
0051     writel_relaxed(val, to_mps2_clkevt(c)->reg + offset);
0052 }
0053
0054 static int mps2_timer_shutdown(struct clock_event_device *ce)
0055 {
0056     clockevent_mps2_writel(0, ce, TIMER_RELOAD);
0057     clockevent_mps2_writel(0, ce, TIMER_CTRL);
0058
0059     return 0;
0060 }
0061
0062 static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce)
0063 {
0064     clockevent_mps2_writel(next, ce, TIMER_VALUE);
0065     clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
0066
0067     return 0;
0068 }
0069
0070 static int mps2_timer_set_periodic(struct clock_event_device *ce)
0071 {
0072     u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick;
0073
0074     clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD);
0075     clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE);
0076     clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
0077
0078     return 0;
0079 }
0080
0081 static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id)
0082 {
0083     struct clockevent_mps2 *ce = dev_id;
0084     u32 status = readl_relaxed(ce->reg + TIMER_INT);
0085
0086     if (!status) {
0087         pr_warn("spurious interrupt\n");
0088         return IRQ_NONE;
0089     }
0090
0091     writel_relaxed(1, ce->reg + TIMER_INT);
0092
0093     ce->clkevt.event_handler(&ce->clkevt);
0094
0095     return IRQ_HANDLED;
0096 }
0097
0098 static int __init mps2_clockevent_init(struct device_node *np)
0099 {
0100     void __iomem *base;
0101     struct clk *clk = NULL;
0102     struct clockevent_mps2 *ce;
0103     u32 rate;
0104     int irq, ret;
0105     const char *name = "mps2-clkevt";
0106
0107     ret = of_property_read_u32(np, "clock-frequency", &rate);
0108     if (ret) {
0109         clk = of_clk_get(np, 0);
0110         if (IS_ERR(clk)) {
0111             ret = PTR_ERR(clk);
0112             pr_err("failed to get clock for clockevent: %d\n", ret);
0113             goto out;
0114         }
0115
0116         ret = clk_prepare_enable(clk);
0117         if (ret) {
0118             pr_err("failed to enable clock for clockevent: %d\n", ret);
0119             goto out_clk_put;
0120         }
0121
0122         rate = clk_get_rate(clk);
0123     }
0124
0125     base = of_iomap(np, 0);
0126     if (!base) {
0127         ret = -EADDRNOTAVAIL;
0128         pr_err("failed to map register for clockevent: %d\n", ret);
0129         goto out_clk_disable;
0130     }
0131
0132     irq = irq_of_parse_and_map(np, 0);
0133     if (!irq) {
0134         ret = -ENOENT;
0135         pr_err("failed to get irq for clockevent: %d\n", ret);
0136         goto out_iounmap;
0137     }
0138
0139     ce = kzalloc(sizeof(*ce), GFP_KERNEL);
0140     if (!ce) {
0141         ret = -ENOMEM;
0142         goto out_iounmap;
0143     }
0144
0145     ce->reg = base;
0146     ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ);
0147     ce->clkevt.irq = irq;
0148     ce->clkevt.name = name;
0149     ce->clkevt.rating = 200;
0150     ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
0151     ce->clkevt.cpumask = cpu_possible_mask;
0152     ce->clkevt.set_state_shutdown   = mps2_timer_shutdown;
0153     ce->clkevt.set_state_periodic   = mps2_timer_set_periodic;
0154     ce->clkevt.set_state_oneshot    = mps2_timer_shutdown;
0155     ce->clkevt.set_next_event   = mps2_timer_set_next_event;
0156
0157     /* Ensure timer is disabled */
0158     writel_relaxed(0, base + TIMER_CTRL);
0159
0160     ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce);
0161     if (ret) {
0162         pr_err("failed to request irq for clockevent: %d\n", ret);
0163         goto out_kfree;
0164     }
0165
0166     clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff);
0167
0168     return 0;
0169
0170 out_kfree:
0171     kfree(ce);
0172 out_iounmap:
0173     iounmap(base);
0174 out_clk_disable:
0175     /* clk_{disable, unprepare, put}() can handle NULL as a parameter */
0176     clk_disable_unprepare(clk);
0177 out_clk_put:
0178     clk_put(clk);
0179 out:
0180     return ret;
0181 }
0182
0183 static int __init mps2_clocksource_init(struct device_node *np)
0184 {
0185     void __iomem *base;
0186     struct clk *clk = NULL;
0187     u32 rate;
0188     int ret;
0189     const char *name = "mps2-clksrc";
0190
0191     ret = of_property_read_u32(np, "clock-frequency", &rate);
0192     if (ret) {
0193         clk = of_clk_get(np, 0);
0194         if (IS_ERR(clk)) {
0195             ret = PTR_ERR(clk);
0196             pr_err("failed to get clock for clocksource: %d\n", ret);
0197             goto out;
0198         }
0199
0200         ret = clk_prepare_enable(clk);
0201         if (ret) {
0202             pr_err("failed to enable clock for clocksource: %d\n", ret);
0203             goto out_clk_put;
0204         }
0205
0206         rate = clk_get_rate(clk);
0207     }
0208
0209     base = of_iomap(np, 0);
0210     if (!base) {
0211         ret = -EADDRNOTAVAIL;
0212         pr_err("failed to map register for clocksource: %d\n", ret);
0213         goto out_clk_disable;
0214     }
0215
0216     /* Ensure timer is disabled */
0217     writel_relaxed(0, base + TIMER_CTRL);
0218
0219     /* ... and set it up as free-running clocksource */
0220     writel_relaxed(0xffffffff, base + TIMER_VALUE);
0221     writel_relaxed(0xffffffff, base + TIMER_RELOAD);
0222
0223     writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL);
0224
0225     ret = clocksource_mmio_init(base + TIMER_VALUE, name,
0226                     rate, 200, 32,
0227                     clocksource_mmio_readl_down);
0228     if (ret) {
0229         pr_err("failed to init clocksource: %d\n", ret);
0230         goto out_iounmap;
0231     }
0232
0233     sched_clock_base = base;
0234     sched_clock_register(mps2_sched_read, 32, rate);
0235
0236     return 0;
0237
0238 out_iounmap:
0239     iounmap(base);
0240 out_clk_disable:
0241     /* clk_{disable, unprepare, put}() can handle NULL as a parameter */
0242     clk_disable_unprepare(clk);
0243 out_clk_put:
0244     clk_put(clk);
0245 out:
0246     return ret;
0247 }
0248
0249 static int __init mps2_timer_init(struct device_node *np)
0250 {
0251     static int has_clocksource, has_clockevent;
0252     int ret;
0253
0254     if (!has_clocksource) {
0255         ret = mps2_clocksource_init(np);
0256         if (!ret) {
0257             has_clocksource = 1;
0258             return 0;
0259         }
0260     }
0261
0262     if (!has_clockevent) {
0263         ret = mps2_clockevent_init(np);
0264         if (!ret) {
0265             has_clockevent = 1;
0266             return 0;
0267         }
0268     }
0269
0270     return 0;
0271 }
0272
0273 TIMER_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);