drivers/clocksource/mips-gic-timer.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
0003
0004 #define pr_fmt(fmt) "mips-gic-timer: " fmt
0005
0006 #include <linux/clk.h>
0007 #include <linux/clockchips.h>
0008 #include <linux/cpu.h>
0009 #include <linux/init.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/notifier.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/percpu.h>
0014 #include <linux/sched_clock.h>
0015 #include <linux/smp.h>
0016 #include <linux/time.h>
0017 #include <asm/mips-cps.h>
0018
0019 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
0020 static int gic_timer_irq;
0021 static unsigned int gic_frequency;
0022 static bool __read_mostly gic_clock_unstable;
0023
0024 static void gic_clocksource_unstable(char *reason);
0025
0026 static u64 notrace gic_read_count_2x32(void)
0027 {
0028     unsigned int hi, hi2, lo;
0029
0030     do {
0031         hi = read_gic_counter_32h();
0032         lo = read_gic_counter_32l();
0033         hi2 = read_gic_counter_32h();
0034     } while (hi2 != hi);
0035
0036     return (((u64) hi) << 32) + lo;
0037 }
0038
0039 static u64 notrace gic_read_count_64(void)
0040 {
0041     return read_gic_counter();
0042 }
0043
0044 static u64 notrace gic_read_count(void)
0045 {
0046     if (mips_cm_is64)
0047         return gic_read_count_64();
0048
0049     return gic_read_count_2x32();
0050 }
0051
0052 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
0053 {
0054     int cpu = cpumask_first(evt->cpumask);
0055     u64 cnt;
0056     int res;
0057
0058     cnt = gic_read_count();
0059     cnt += (u64)delta;
0060     if (cpu == raw_smp_processor_id()) {
0061         write_gic_vl_compare(cnt);
0062     } else {
0063         write_gic_vl_other(mips_cm_vp_id(cpu));
0064         write_gic_vo_compare(cnt);
0065     }
0066     res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
0067     return res;
0068 }
0069
0070 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
0071 {
0072     struct clock_event_device *cd = dev_id;
0073
0074     write_gic_vl_compare(read_gic_vl_compare());
0075     cd->event_handler(cd);
0076     return IRQ_HANDLED;
0077 }
0078
0079 static struct irqaction gic_compare_irqaction = {
0080     .handler = gic_compare_interrupt,
0081     .percpu_dev_id = &gic_clockevent_device,
0082     .flags = IRQF_PERCPU | IRQF_TIMER,
0083     .name = "timer",
0084 };
0085
0086 static void gic_clockevent_cpu_init(unsigned int cpu,
0087                     struct clock_event_device *cd)
0088 {
0089     cd->name        = "MIPS GIC";
0090     cd->features        = CLOCK_EVT_FEAT_ONESHOT |
0091                   CLOCK_EVT_FEAT_C3STOP;
0092
0093     cd->rating      = 350;
0094     cd->irq         = gic_timer_irq;
0095     cd->cpumask     = cpumask_of(cpu);
0096     cd->set_next_event  = gic_next_event;
0097
0098     clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
0099
0100     enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
0101 }
0102
0103 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
0104 {
0105     disable_percpu_irq(gic_timer_irq);
0106 }
0107
0108 static void gic_update_frequency(void *data)
0109 {
0110     unsigned long rate = (unsigned long)data;
0111
0112     clockevents_update_freq(this_cpu_ptr(&gic_clockevent_device), rate);
0113 }
0114
0115 static int gic_starting_cpu(unsigned int cpu)
0116 {
0117     gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device));
0118     return 0;
0119 }
0120
0121 static int gic_clk_notifier(struct notifier_block *nb, unsigned long action,
0122                 void *data)
0123 {
0124     struct clk_notifier_data *cnd = data;
0125
0126     if (action == POST_RATE_CHANGE) {
0127         gic_clocksource_unstable("ref clock rate change");
0128         on_each_cpu(gic_update_frequency, (void *)cnd->new_rate, 1);
0129     }
0130
0131     return NOTIFY_OK;
0132 }
0133
0134 static int gic_dying_cpu(unsigned int cpu)
0135 {
0136     gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
0137     return 0;
0138 }
0139
0140 static struct notifier_block gic_clk_nb = {
0141     .notifier_call = gic_clk_notifier,
0142 };
0143
0144 static int gic_clockevent_init(void)
0145 {
0146     int ret;
0147
0148     if (!gic_frequency)
0149         return -ENXIO;
0150
0151     ret = setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
0152     if (ret < 0) {
0153         pr_err("IRQ %d setup failed (%d)\n", gic_timer_irq, ret);
0154         return ret;
0155     }
0156
0157     cpuhp_setup_state(CPUHP_AP_MIPS_GIC_TIMER_STARTING,
0158               "clockevents/mips/gic/timer:starting",
0159               gic_starting_cpu, gic_dying_cpu);
0160     return 0;
0161 }
0162
0163 static u64 gic_hpt_read(struct clocksource *cs)
0164 {
0165     return gic_read_count();
0166 }
0167
0168 static struct clocksource gic_clocksource = {
0169     .name           = "GIC",
0170     .read           = gic_hpt_read,
0171     .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
0172     .vdso_clock_mode    = VDSO_CLOCKMODE_GIC,
0173 };
0174
0175 static void gic_clocksource_unstable(char *reason)
0176 {
0177     if (gic_clock_unstable)
0178         return;
0179
0180     gic_clock_unstable = true;
0181
0182     pr_info("GIC timer is unstable due to %s\n", reason);
0183
0184     clocksource_mark_unstable(&gic_clocksource);
0185 }
0186
0187 static int __init __gic_clocksource_init(void)
0188 {
0189     unsigned int count_width;
0190     int ret;
0191
0192     /* Set clocksource mask. */
0193     count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
0194     count_width >>= __ffs(GIC_CONFIG_COUNTBITS);
0195     count_width *= 4;
0196     count_width += 32;
0197     gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
0198
0199     /* Calculate a somewhat reasonable rating value. */
0200     gic_clocksource.rating = 200 + gic_frequency / 10000000;
0201
0202     ret = clocksource_register_hz(&gic_clocksource, gic_frequency);
0203     if (ret < 0)
0204         pr_warn("Unable to register clocksource\n");
0205
0206     return ret;
0207 }
0208
0209 static int __init gic_clocksource_of_init(struct device_node *node)
0210 {
0211     struct clk *clk;
0212     int ret;
0213
0214     if (!mips_gic_present() || !node->parent ||
0215         !of_device_is_compatible(node->parent, "mti,gic")) {
0216         pr_warn("No DT definition\n");
0217         return -ENXIO;
0218     }
0219
0220     clk = of_clk_get(node, 0);
0221     if (!IS_ERR(clk)) {
0222         ret = clk_prepare_enable(clk);
0223         if (ret < 0) {
0224             pr_err("Failed to enable clock\n");
0225             clk_put(clk);
0226             return ret;
0227         }
0228
0229         gic_frequency = clk_get_rate(clk);
0230     } else if (of_property_read_u32(node, "clock-frequency",
0231                     &gic_frequency)) {
0232         pr_err("Frequency not specified\n");
0233         return -EINVAL;
0234     }
0235     gic_timer_irq = irq_of_parse_and_map(node, 0);
0236     if (!gic_timer_irq) {
0237         pr_err("IRQ not specified\n");
0238         return -EINVAL;
0239     }
0240
0241     ret = __gic_clocksource_init();
0242     if (ret)
0243         return ret;
0244
0245     ret = gic_clockevent_init();
0246     if (!ret && !IS_ERR(clk)) {
0247         if (clk_notifier_register(clk, &gic_clk_nb) < 0)
0248             pr_warn("Unable to register clock notifier\n");
0249     }
0250
0251     /* And finally start the counter */
0252     clear_gic_config(GIC_CONFIG_COUNTSTOP);
0253
0254     /*
0255      * It's safe to use the MIPS GIC timer as a sched clock source only if
0256      * its ticks are stable, which is true on either the platforms with
0257      * stable CPU frequency or on the platforms with CM3 and CPU frequency
0258      * change performed by the CPC core clocks divider.
0259      */
0260     if (mips_cm_revision() >= CM_REV_CM3 || !IS_ENABLED(CONFIG_CPU_FREQ)) {
0261         sched_clock_register(mips_cm_is64 ?
0262                      gic_read_count_64 : gic_read_count_2x32,
0263                      64, gic_frequency);
0264     }
0265
0266     return 0;
0267 }
0268 TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
0269                gic_clocksource_of_init);