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0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/clockchips.h>
0018
0019 #define RATE_32K 32768
0020
0021 #define TIMER_MODE_CONTINUOUS 0x1
0022 #define TIMER_DOWNCOUNT_VAL 0xffffffff
0023
0024 #define PRCMU_TIMER_REF 0
0025 #define PRCMU_TIMER_DOWNCOUNT 0x4
0026 #define PRCMU_TIMER_MODE 0x8
0027
0028 static void __iomem *clksrc_dbx500_timer_base;
0029
0030 static u64 notrace clksrc_dbx500_prcmu_read(struct clocksource *cs)
0031 {
0032 void __iomem *base = clksrc_dbx500_timer_base;
0033 u32 count, count2;
0034
0035 do {
0036 count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
0037 count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT);
0038 } while (count2 != count);
0039
0040
0041 return ~count;
0042 }
0043
0044 static struct clocksource clocksource_dbx500_prcmu = {
0045 .name = "dbx500-prcmu-timer",
0046 .rating = 100,
0047 .read = clksrc_dbx500_prcmu_read,
0048 .mask = CLOCKSOURCE_MASK(32),
0049 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
0050 };
0051
0052 static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
0053 {
0054 clksrc_dbx500_timer_base = of_iomap(node, 0);
0055
0056
0057
0058
0059
0060
0061
0062 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
0063 TIMER_MODE_CONTINUOUS) {
0064 writel(TIMER_MODE_CONTINUOUS,
0065 clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
0066 writel(TIMER_DOWNCOUNT_VAL,
0067 clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
0068 }
0069 return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
0070 }
0071 TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
0072 clksrc_dbx500_prcmu_init);