drivers/clocksource/asm9260_timer.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
0004  */
0005
0006 #include <linux/kernel.h>
0007 #include <linux/init.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/sched.h>
0010 #include <linux/clk.h>
0011 #include <linux/clocksource.h>
0012 #include <linux/clockchips.h>
0013 #include <linux/io.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/bitops.h>
0018
0019 #define DRIVER_NAME "asm9260-timer"
0020
0021 /*
0022  * this device provide 4 offsets for each register:
0023  * 0x0 - plain read write mode
0024  * 0x4 - set mode, OR logic.
0025  * 0x8 - clr mode, XOR logic.
0026  * 0xc - togle mode.
0027  */
0028 #define SET_REG 4
0029 #define CLR_REG 8
0030
0031 #define HW_IR           0x0000 /* RW. Interrupt */
0032 #define BM_IR_CR0   BIT(4)
0033 #define BM_IR_MR3   BIT(3)
0034 #define BM_IR_MR2   BIT(2)
0035 #define BM_IR_MR1   BIT(1)
0036 #define BM_IR_MR0   BIT(0)
0037
0038 #define HW_TCR      0x0010 /* RW. Timer controller */
0039 /* BM_C*_RST
0040  * Timer Counter and the Prescale Counter are synchronously reset on the
0041  * next positive edge of PCLK. The counters remain reset until TCR[1] is
0042  * returned to zero. */
0043 #define BM_C3_RST   BIT(7)
0044 #define BM_C2_RST   BIT(6)
0045 #define BM_C1_RST   BIT(5)
0046 #define BM_C0_RST   BIT(4)
0047 /* BM_C*_EN
0048  * 1 - Timer Counter and Prescale Counter are enabled for counting
0049  * 0 - counters are disabled */
0050 #define BM_C3_EN    BIT(3)
0051 #define BM_C2_EN    BIT(2)
0052 #define BM_C1_EN    BIT(1)
0053 #define BM_C0_EN    BIT(0)
0054
0055 #define HW_DIR      0x0020 /* RW. Direction? */
0056 /* 00 - count up
0057  * 01 - count down
0058  * 10 - ?? 2^n/2 */
0059 #define BM_DIR_COUNT_UP     0
0060 #define BM_DIR_COUNT_DOWN   1
0061 #define BM_DIR0_SHIFT   0
0062 #define BM_DIR1_SHIFT   4
0063 #define BM_DIR2_SHIFT   8
0064 #define BM_DIR3_SHIFT   12
0065 #define BM_DIR_DEFAULT      (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \
0066                  BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \
0067                  BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \
0068                  BM_DIR_COUNT_UP << BM_DIR3_SHIFT)
0069
0070 #define HW_TC0      0x0030 /* RO. Timer counter 0 */
0071 /* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
0072  * interrupt. This registers can be used to detect overflow */
0073 #define HW_TC1          0x0040
0074 #define HW_TC2      0x0050
0075 #define HW_TC3      0x0060
0076
0077 #define HW_PR       0x0070 /* RW. prescaler */
0078 #define BM_PR_DISABLE   0
0079 #define HW_PC       0x0080 /* RO. Prescaler counter */
0080 #define HW_MCR      0x0090 /* RW. Match control */
0081 /* enable interrupt on match */
0082 #define BM_MCR_INT_EN(n)    (1 << (n * 3 + 0))
0083 /* enable TC reset on match */
0084 #define BM_MCR_RES_EN(n)    (1 << (n * 3 + 1))
0085 /* enable stop TC on match */
0086 #define BM_MCR_STOP_EN(n)   (1 << (n * 3 + 2))
0087
0088 #define HW_MR0      0x00a0 /* RW. Match reg */
0089 #define HW_MR1      0x00b0
0090 #define HW_MR2      0x00C0
0091 #define HW_MR3      0x00D0
0092
0093 #define HW_CTCR     0x0180 /* Counter control */
0094 #define BM_CTCR0_SHIFT  0
0095 #define BM_CTCR1_SHIFT  2
0096 #define BM_CTCR2_SHIFT  4
0097 #define BM_CTCR3_SHIFT  6
0098 #define BM_CTCR_TM  0   /* Timer mode. Every rising PCLK edge. */
0099 #define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \
0100              BM_CTCR_TM << BM_CTCR1_SHIFT | \
0101              BM_CTCR_TM << BM_CTCR2_SHIFT | \
0102              BM_CTCR_TM << BM_CTCR3_SHIFT)
0103
0104 static struct asm9260_timer_priv {
0105     void __iomem *base;
0106     unsigned long ticks_per_jiffy;
0107 } priv;
0108
0109 static int asm9260_timer_set_next_event(unsigned long delta,
0110                      struct clock_event_device *evt)
0111 {
0112     /* configure match count for TC0 */
0113     writel_relaxed(delta, priv.base + HW_MR0);
0114     /* enable TC0 */
0115     writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
0116     return 0;
0117 }
0118
0119 static inline void __asm9260_timer_shutdown(struct clock_event_device *evt)
0120 {
0121     /* stop timer0 */
0122     writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
0123 }
0124
0125 static int asm9260_timer_shutdown(struct clock_event_device *evt)
0126 {
0127     __asm9260_timer_shutdown(evt);
0128     return 0;
0129 }
0130
0131 static int asm9260_timer_set_oneshot(struct clock_event_device *evt)
0132 {
0133     __asm9260_timer_shutdown(evt);
0134
0135     /* enable reset and stop on match */
0136     writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
0137                priv.base + HW_MCR + SET_REG);
0138     return 0;
0139 }
0140
0141 static int asm9260_timer_set_periodic(struct clock_event_device *evt)
0142 {
0143     __asm9260_timer_shutdown(evt);
0144
0145     /* disable reset and stop on match */
0146     writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
0147                priv.base + HW_MCR + CLR_REG);
0148     /* configure match count for TC0 */
0149     writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
0150     /* enable TC0 */
0151     writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
0152     return 0;
0153 }
0154
0155 static struct clock_event_device event_dev = {
0156     .name           = DRIVER_NAME,
0157     .rating         = 200,
0158     .features       = CLOCK_EVT_FEAT_PERIODIC |
0159                   CLOCK_EVT_FEAT_ONESHOT,
0160     .set_next_event     = asm9260_timer_set_next_event,
0161     .set_state_shutdown = asm9260_timer_shutdown,
0162     .set_state_periodic = asm9260_timer_set_periodic,
0163     .set_state_oneshot  = asm9260_timer_set_oneshot,
0164     .tick_resume        = asm9260_timer_shutdown,
0165 };
0166
0167 static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id)
0168 {
0169     struct clock_event_device *evt = dev_id;
0170
0171     evt->event_handler(evt);
0172
0173     writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
0174
0175     return IRQ_HANDLED;
0176 }
0177
0178 /*
0179  * ---------------------------------------------------------------------------
0180  * Timer initialization
0181  * ---------------------------------------------------------------------------
0182  */
0183 static int __init asm9260_timer_init(struct device_node *np)
0184 {
0185     int irq;
0186     struct clk *clk;
0187     int ret;
0188     unsigned long rate;
0189
0190     priv.base = of_io_request_and_map(np, 0, np->name);
0191     if (IS_ERR(priv.base)) {
0192         pr_err("%pOFn: unable to map resource\n", np);
0193         return PTR_ERR(priv.base);
0194     }
0195
0196     clk = of_clk_get(np, 0);
0197     if (IS_ERR(clk)) {
0198         pr_err("Failed to get clk!\n");
0199         return PTR_ERR(clk);
0200     }
0201
0202     ret = clk_prepare_enable(clk);
0203     if (ret) {
0204         pr_err("Failed to enable clk!\n");
0205         return ret;
0206     }
0207
0208     irq = irq_of_parse_and_map(np, 0);
0209     ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER,
0210             DRIVER_NAME, &event_dev);
0211     if (ret) {
0212         pr_err("Failed to setup irq!\n");
0213         return ret;
0214     }
0215
0216     /* set all timers for count-up */
0217     writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
0218     /* disable divider */
0219     writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
0220     /* make sure all timers use every rising PCLK edge. */
0221     writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
0222     /* enable interrupt for TC0 and clean setting for all other lines */
0223     writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
0224
0225     rate = clk_get_rate(clk);
0226     clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
0227             200, 32, clocksource_mmio_readl_up);
0228
0229     /* Seems like we can't use counter without match register even if
0230      * actions for MR are disabled. So, set MR to max value. */
0231     writel_relaxed(0xffffffff, priv.base + HW_MR1);
0232     /* enable TC1 */
0233     writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
0234
0235     priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
0236     event_dev.cpumask = cpumask_of(0);
0237     clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe);
0238
0239     return 0;
0240 }
0241 TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
0242         asm9260_timer_init);