drivers/clocksource/arm_global_timer.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * drivers/clocksource/arm_global_timer.c
0004  *
0005  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
0006  * Author: Stuart Menefy <stuart.menefy@st.com>
0007  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
0008  */
0009
0010 #include <linux/init.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/clocksource.h>
0013 #include <linux/clockchips.h>
0014 #include <linux/cpu.h>
0015 #include <linux/clk.h>
0016 #include <linux/delay.h>
0017 #include <linux/err.h>
0018 #include <linux/io.h>
0019 #include <linux/of.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/of_address.h>
0022 #include <linux/sched_clock.h>
0023
0024 #include <asm/cputype.h>
0025
0026 #define GT_COUNTER0 0x00
0027 #define GT_COUNTER1 0x04
0028
0029 #define GT_CONTROL  0x08
0030 #define GT_CONTROL_TIMER_ENABLE     BIT(0)  /* this bit is NOT banked */
0031 #define GT_CONTROL_COMP_ENABLE      BIT(1)  /* banked */
0032 #define GT_CONTROL_IRQ_ENABLE       BIT(2)  /* banked */
0033 #define GT_CONTROL_AUTO_INC     BIT(3)  /* banked */
0034 #define GT_CONTROL_PRESCALER_SHIFT      8
0035 #define GT_CONTROL_PRESCALER_MAX        0xF
0036 #define GT_CONTROL_PRESCALER_MASK       (GT_CONTROL_PRESCALER_MAX << \
0037                      GT_CONTROL_PRESCALER_SHIFT)
0038
0039 #define GT_INT_STATUS   0x0c
0040 #define GT_INT_STATUS_EVENT_FLAG    BIT(0)
0041
0042 #define GT_COMP0    0x10
0043 #define GT_COMP1    0x14
0044 #define GT_AUTO_INC 0x18
0045
0046 #define MAX_F_ERR 50
0047 /*
0048  * We are expecting to be clocked by the ARM peripheral clock.
0049  *
0050  * Note: it is assumed we are using a prescaler value of zero, so this is
0051  * the units for all operations.
0052  */
0053 static void __iomem *gt_base;
0054 static struct notifier_block gt_clk_rate_change_nb;
0055 static u32 gt_psv_new, gt_psv_bck, gt_target_rate;
0056 static int gt_ppi;
0057 static struct clock_event_device __percpu *gt_evt;
0058
0059 /*
0060  * To get the value from the Global Timer Counter register proceed as follows:
0061  * 1. Read the upper 32-bit timer counter register
0062  * 2. Read the lower 32-bit timer counter register
0063  * 3. Read the upper 32-bit timer counter register again. If the value is
0064  *  different to the 32-bit upper value read previously, go back to step 2.
0065  *  Otherwise the 64-bit timer counter value is correct.
0066  */
0067 static u64 notrace _gt_counter_read(void)
0068 {
0069     u64 counter;
0070     u32 lower;
0071     u32 upper, old_upper;
0072
0073     upper = readl_relaxed(gt_base + GT_COUNTER1);
0074     do {
0075         old_upper = upper;
0076         lower = readl_relaxed(gt_base + GT_COUNTER0);
0077         upper = readl_relaxed(gt_base + GT_COUNTER1);
0078     } while (upper != old_upper);
0079
0080     counter = upper;
0081     counter <<= 32;
0082     counter |= lower;
0083     return counter;
0084 }
0085
0086 static u64 gt_counter_read(void)
0087 {
0088     return _gt_counter_read();
0089 }
0090
0091 /**
0092  * To ensure that updates to comparator value register do not set the
0093  * Interrupt Status Register proceed as follows:
0094  * 1. Clear the Comp Enable bit in the Timer Control Register.
0095  * 2. Write the lower 32-bit Comparator Value Register.
0096  * 3. Write the upper 32-bit Comparator Value Register.
0097  * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
0098  */
0099 static void gt_compare_set(unsigned long delta, int periodic)
0100 {
0101     u64 counter = gt_counter_read();
0102     unsigned long ctrl;
0103
0104     counter += delta;
0105     ctrl = readl(gt_base + GT_CONTROL);
0106     ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
0107           GT_CONTROL_AUTO_INC);
0108     ctrl |= GT_CONTROL_TIMER_ENABLE;
0109     writel_relaxed(ctrl, gt_base + GT_CONTROL);
0110     writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
0111     writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
0112
0113     if (periodic) {
0114         writel_relaxed(delta, gt_base + GT_AUTO_INC);
0115         ctrl |= GT_CONTROL_AUTO_INC;
0116     }
0117
0118     ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
0119     writel_relaxed(ctrl, gt_base + GT_CONTROL);
0120 }
0121
0122 static int gt_clockevent_shutdown(struct clock_event_device *evt)
0123 {
0124     unsigned long ctrl;
0125
0126     ctrl = readl(gt_base + GT_CONTROL);
0127     ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
0128           GT_CONTROL_AUTO_INC);
0129     writel(ctrl, gt_base + GT_CONTROL);
0130     return 0;
0131 }
0132
0133 static int gt_clockevent_set_periodic(struct clock_event_device *evt)
0134 {
0135     gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), 1);
0136     return 0;
0137 }
0138
0139 static int gt_clockevent_set_next_event(unsigned long evt,
0140                     struct clock_event_device *unused)
0141 {
0142     gt_compare_set(evt, 0);
0143     return 0;
0144 }
0145
0146 static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
0147 {
0148     struct clock_event_device *evt = dev_id;
0149
0150     if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
0151                 GT_INT_STATUS_EVENT_FLAG))
0152         return IRQ_NONE;
0153
0154     /**
0155      * ERRATA 740657( Global Timer can send 2 interrupts for
0156      * the same event in single-shot mode)
0157      * Workaround:
0158      *  Either disable single-shot mode.
0159      *  Or
0160      *  Modify the Interrupt Handler to avoid the
0161      *  offending sequence. This is achieved by clearing
0162      *  the Global Timer flag _after_ having incremented
0163      *  the Comparator register value to a higher value.
0164      */
0165     if (clockevent_state_oneshot(evt))
0166         gt_compare_set(ULONG_MAX, 0);
0167
0168     writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
0169     evt->event_handler(evt);
0170
0171     return IRQ_HANDLED;
0172 }
0173
0174 static int gt_starting_cpu(unsigned int cpu)
0175 {
0176     struct clock_event_device *clk = this_cpu_ptr(gt_evt);
0177
0178     clk->name = "arm_global_timer";
0179     clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
0180         CLOCK_EVT_FEAT_PERCPU;
0181     clk->set_state_shutdown = gt_clockevent_shutdown;
0182     clk->set_state_periodic = gt_clockevent_set_periodic;
0183     clk->set_state_oneshot = gt_clockevent_shutdown;
0184     clk->set_state_oneshot_stopped = gt_clockevent_shutdown;
0185     clk->set_next_event = gt_clockevent_set_next_event;
0186     clk->cpumask = cpumask_of(cpu);
0187     clk->rating = 300;
0188     clk->irq = gt_ppi;
0189     clockevents_config_and_register(clk, gt_target_rate,
0190                     1, 0xffffffff);
0191     enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
0192     return 0;
0193 }
0194
0195 static int gt_dying_cpu(unsigned int cpu)
0196 {
0197     struct clock_event_device *clk = this_cpu_ptr(gt_evt);
0198
0199     gt_clockevent_shutdown(clk);
0200     disable_percpu_irq(clk->irq);
0201     return 0;
0202 }
0203
0204 static u64 gt_clocksource_read(struct clocksource *cs)
0205 {
0206     return gt_counter_read();
0207 }
0208
0209 static void gt_resume(struct clocksource *cs)
0210 {
0211     unsigned long ctrl;
0212
0213     ctrl = readl(gt_base + GT_CONTROL);
0214     if (!(ctrl & GT_CONTROL_TIMER_ENABLE))
0215         /* re-enable timer on resume */
0216         writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
0217 }
0218
0219 static struct clocksource gt_clocksource = {
0220     .name   = "arm_global_timer",
0221     .rating = 300,
0222     .read   = gt_clocksource_read,
0223     .mask   = CLOCKSOURCE_MASK(64),
0224     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0225     .resume = gt_resume,
0226 };
0227
0228 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
0229 static u64 notrace gt_sched_clock_read(void)
0230 {
0231     return _gt_counter_read();
0232 }
0233 #endif
0234
0235 static unsigned long gt_read_long(void)
0236 {
0237     return readl_relaxed(gt_base + GT_COUNTER0);
0238 }
0239
0240 static struct delay_timer gt_delay_timer = {
0241     .read_current_timer = gt_read_long,
0242 };
0243
0244 static void gt_write_presc(u32 psv)
0245 {
0246     u32 reg;
0247
0248     reg = readl(gt_base + GT_CONTROL);
0249     reg &= ~GT_CONTROL_PRESCALER_MASK;
0250     reg |= psv << GT_CONTROL_PRESCALER_SHIFT;
0251     writel(reg, gt_base + GT_CONTROL);
0252 }
0253
0254 static u32 gt_read_presc(void)
0255 {
0256     u32 reg;
0257
0258     reg = readl(gt_base + GT_CONTROL);
0259     reg &= GT_CONTROL_PRESCALER_MASK;
0260     return reg >> GT_CONTROL_PRESCALER_SHIFT;
0261 }
0262
0263 static void __init gt_delay_timer_init(void)
0264 {
0265     gt_delay_timer.freq = gt_target_rate;
0266     register_current_timer_delay(&gt_delay_timer);
0267 }
0268
0269 static int __init gt_clocksource_init(void)
0270 {
0271     writel(0, gt_base + GT_CONTROL);
0272     writel(0, gt_base + GT_COUNTER0);
0273     writel(0, gt_base + GT_COUNTER1);
0274     /* set prescaler and enable timer on all the cores */
0275     writel(((CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) <<
0276         GT_CONTROL_PRESCALER_SHIFT)
0277            | GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
0278
0279 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
0280     sched_clock_register(gt_sched_clock_read, 64, gt_target_rate);
0281 #endif
0282     return clocksource_register_hz(&gt_clocksource, gt_target_rate);
0283 }
0284
0285 static int gt_clk_rate_change_cb(struct notifier_block *nb,
0286                  unsigned long event, void *data)
0287 {
0288     struct clk_notifier_data *ndata = data;
0289
0290     switch (event) {
0291     case PRE_RATE_CHANGE:
0292     {
0293         int psv;
0294
0295         psv = DIV_ROUND_CLOSEST(ndata->new_rate,
0296                     gt_target_rate);
0297
0298         if (abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)
0299             return NOTIFY_BAD;
0300
0301         psv--;
0302
0303         /* prescaler within legal range? */
0304         if (psv < 0 || psv > GT_CONTROL_PRESCALER_MAX)
0305             return NOTIFY_BAD;
0306
0307         /*
0308          * store timer clock ctrl register so we can restore it in case
0309          * of an abort.
0310          */
0311         gt_psv_bck = gt_read_presc();
0312         gt_psv_new = psv;
0313         /* scale down: adjust divider in post-change notification */
0314         if (ndata->new_rate < ndata->old_rate)
0315             return NOTIFY_DONE;
0316
0317         /* scale up: adjust divider now - before frequency change */
0318         gt_write_presc(psv);
0319         break;
0320     }
0321     case POST_RATE_CHANGE:
0322         /* scale up: pre-change notification did the adjustment */
0323         if (ndata->new_rate > ndata->old_rate)
0324             return NOTIFY_OK;
0325
0326         /* scale down: adjust divider now - after frequency change */
0327         gt_write_presc(gt_psv_new);
0328         break;
0329
0330     case ABORT_RATE_CHANGE:
0331         /* we have to undo the adjustment in case we scale up */
0332         if (ndata->new_rate < ndata->old_rate)
0333             return NOTIFY_OK;
0334
0335         /* restore original register value */
0336         gt_write_presc(gt_psv_bck);
0337         break;
0338     default:
0339         return NOTIFY_DONE;
0340     }
0341
0342     return NOTIFY_DONE;
0343 }
0344
0345 static int __init global_timer_of_register(struct device_node *np)
0346 {
0347     struct clk *gt_clk;
0348     static unsigned long gt_clk_rate;
0349     int err = 0;
0350
0351     /*
0352      * In A9 r2p0 the comparators for each processor with the global timer
0353      * fire when the timer value is greater than or equal to. In previous
0354      * revisions the comparators fired when the timer value was equal to.
0355      */
0356     if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
0357         && (read_cpuid_id() & 0xf0000f) < 0x200000) {
0358         pr_warn("global-timer: non support for this cpu version.\n");
0359         return -ENOSYS;
0360     }
0361
0362     gt_ppi = irq_of_parse_and_map(np, 0);
0363     if (!gt_ppi) {
0364         pr_warn("global-timer: unable to parse irq\n");
0365         return -EINVAL;
0366     }
0367
0368     gt_base = of_iomap(np, 0);
0369     if (!gt_base) {
0370         pr_warn("global-timer: invalid base address\n");
0371         return -ENXIO;
0372     }
0373
0374     gt_clk = of_clk_get(np, 0);
0375     if (!IS_ERR(gt_clk)) {
0376         err = clk_prepare_enable(gt_clk);
0377         if (err)
0378             goto out_unmap;
0379     } else {
0380         pr_warn("global-timer: clk not found\n");
0381         err = -EINVAL;
0382         goto out_unmap;
0383     }
0384
0385     gt_clk_rate = clk_get_rate(gt_clk);
0386     gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL;
0387     gt_clk_rate_change_nb.notifier_call =
0388         gt_clk_rate_change_cb;
0389     err = clk_notifier_register(gt_clk, &gt_clk_rate_change_nb);
0390     if (err) {
0391         pr_warn("Unable to register clock notifier\n");
0392         goto out_clk;
0393     }
0394
0395     gt_evt = alloc_percpu(struct clock_event_device);
0396     if (!gt_evt) {
0397         pr_warn("global-timer: can't allocate memory\n");
0398         err = -ENOMEM;
0399         goto out_clk_nb;
0400     }
0401
0402     err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
0403                  "gt", gt_evt);
0404     if (err) {
0405         pr_warn("global-timer: can't register interrupt %d (%d)\n",
0406             gt_ppi, err);
0407         goto out_free;
0408     }
0409
0410     /* Register and immediately configure the timer on the boot CPU */
0411     err = gt_clocksource_init();
0412     if (err)
0413         goto out_irq;
0414
0415     err = cpuhp_setup_state(CPUHP_AP_ARM_GLOBAL_TIMER_STARTING,
0416                 "clockevents/arm/global_timer:starting",
0417                 gt_starting_cpu, gt_dying_cpu);
0418     if (err)
0419         goto out_irq;
0420
0421     gt_delay_timer_init();
0422
0423     return 0;
0424
0425 out_irq:
0426     free_percpu_irq(gt_ppi, gt_evt);
0427 out_free:
0428     free_percpu(gt_evt);
0429 out_clk_nb:
0430     clk_notifier_unregister(gt_clk, &gt_clk_rate_change_nb);
0431 out_clk:
0432     clk_disable_unprepare(gt_clk);
0433 out_unmap:
0434     iounmap(gt_base);
0435     WARN(err, "ARM Global timer register failed (%d)\n", err);
0436
0437     return err;
0438 }
0439
0440 /* Only tested on r2p2 and r3p0  */
0441 TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
0442             global_timer_of_register);