drivers/clocksource/arc_timer.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
0004  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
0005  */
0006
0007 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
0008  * programmed to go from @count to @limit and optionally interrupt.
0009  * We've designated TIMER0 for clockevents and TIMER1 for clocksource
0010  *
0011  * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
0012  * which are suitable for UP and SMP based clocksources respectively
0013  */
0014
0015 #include <linux/interrupt.h>
0016 #include <linux/bits.h>
0017 #include <linux/clk.h>
0018 #include <linux/clk-provider.h>
0019 #include <linux/clocksource.h>
0020 #include <linux/clockchips.h>
0021 #include <linux/cpu.h>
0022 #include <linux/of.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/sched_clock.h>
0025
0026 #include <soc/arc/timers.h>
0027 #include <soc/arc/mcip.h>
0028
0029
0030 static unsigned long arc_timer_freq;
0031
0032 static int noinline arc_get_timer_clk(struct device_node *node)
0033 {
0034     struct clk *clk;
0035     int ret;
0036
0037     clk = of_clk_get(node, 0);
0038     if (IS_ERR(clk)) {
0039         pr_err("timer missing clk\n");
0040         return PTR_ERR(clk);
0041     }
0042
0043     ret = clk_prepare_enable(clk);
0044     if (ret) {
0045         pr_err("Couldn't enable parent clk\n");
0046         return ret;
0047     }
0048
0049     arc_timer_freq = clk_get_rate(clk);
0050
0051     return 0;
0052 }
0053
0054 /********** Clock Source Device *********/
0055
0056 #ifdef CONFIG_ARC_TIMERS_64BIT
0057
0058 static u64 arc_read_gfrc(struct clocksource *cs)
0059 {
0060     unsigned long flags;
0061     u32 l, h;
0062
0063     /*
0064      * From a programming model pov, there seems to be just one instance of
0065      * MCIP_CMD/MCIP_READBACK however micro-architecturally there's
0066      * an instance PER ARC CORE (not per cluster), and there are dedicated
0067      * hardware decode logic (per core) inside ARConnect to handle
0068      * simultaneous read/write accesses from cores via those two registers.
0069      * So several concurrent commands to ARConnect are OK if they are
0070      * trying to access two different sub-components (like GFRC,
0071      * inter-core interrupt, etc...). HW also supports simultaneously
0072      * accessing GFRC by multiple cores.
0073      * That's why it is safe to disable hard interrupts on the local CPU
0074      * before access to GFRC instead of taking global MCIP spinlock
0075      * defined in arch/arc/kernel/mcip.c
0076      */
0077     local_irq_save(flags);
0078
0079     __mcip_cmd(CMD_GFRC_READ_LO, 0);
0080     l = read_aux_reg(ARC_REG_MCIP_READBACK);
0081
0082     __mcip_cmd(CMD_GFRC_READ_HI, 0);
0083     h = read_aux_reg(ARC_REG_MCIP_READBACK);
0084
0085     local_irq_restore(flags);
0086
0087     return (((u64)h) << 32) | l;
0088 }
0089
0090 static notrace u64 arc_gfrc_clock_read(void)
0091 {
0092     return arc_read_gfrc(NULL);
0093 }
0094
0095 static struct clocksource arc_counter_gfrc = {
0096     .name   = "ARConnect GFRC",
0097     .rating = 400,
0098     .read   = arc_read_gfrc,
0099     .mask   = CLOCKSOURCE_MASK(64),
0100     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0101 };
0102
0103 static int __init arc_cs_setup_gfrc(struct device_node *node)
0104 {
0105     struct mcip_bcr mp;
0106     int ret;
0107
0108     READ_BCR(ARC_REG_MCIP_BCR, mp);
0109     if (!mp.gfrc) {
0110         pr_warn("Global-64-bit-Ctr clocksource not detected\n");
0111         return -ENXIO;
0112     }
0113
0114     ret = arc_get_timer_clk(node);
0115     if (ret)
0116         return ret;
0117
0118     sched_clock_register(arc_gfrc_clock_read, 64, arc_timer_freq);
0119
0120     return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
0121 }
0122 TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
0123
0124 #define AUX_RTC_CTRL    0x103
0125 #define AUX_RTC_LOW 0x104
0126 #define AUX_RTC_HIGH    0x105
0127
0128 static u64 arc_read_rtc(struct clocksource *cs)
0129 {
0130     unsigned long status;
0131     u32 l, h;
0132
0133     /*
0134      * hardware has an internal state machine which tracks readout of
0135      * low/high and updates the CTRL.status if
0136      *  - interrupt/exception taken between the two reads
0137      *  - high increments after low has been read
0138      */
0139     do {
0140         l = read_aux_reg(AUX_RTC_LOW);
0141         h = read_aux_reg(AUX_RTC_HIGH);
0142         status = read_aux_reg(AUX_RTC_CTRL);
0143     } while (!(status & BIT(31)));
0144
0145     return (((u64)h) << 32) | l;
0146 }
0147
0148 static notrace u64 arc_rtc_clock_read(void)
0149 {
0150     return arc_read_rtc(NULL);
0151 }
0152
0153 static struct clocksource arc_counter_rtc = {
0154     .name   = "ARCv2 RTC",
0155     .rating = 350,
0156     .read   = arc_read_rtc,
0157     .mask   = CLOCKSOURCE_MASK(64),
0158     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0159 };
0160
0161 static int __init arc_cs_setup_rtc(struct device_node *node)
0162 {
0163     struct bcr_timer timer;
0164     int ret;
0165
0166     READ_BCR(ARC_REG_TIMERS_BCR, timer);
0167     if (!timer.rtc) {
0168         pr_warn("Local-64-bit-Ctr clocksource not detected\n");
0169         return -ENXIO;
0170     }
0171
0172     /* Local to CPU hence not usable in SMP */
0173     if (IS_ENABLED(CONFIG_SMP)) {
0174         pr_warn("Local-64-bit-Ctr not usable in SMP\n");
0175         return -EINVAL;
0176     }
0177
0178     ret = arc_get_timer_clk(node);
0179     if (ret)
0180         return ret;
0181
0182     write_aux_reg(AUX_RTC_CTRL, 1);
0183
0184     sched_clock_register(arc_rtc_clock_read, 64, arc_timer_freq);
0185
0186     return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
0187 }
0188 TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
0189
0190 #endif
0191
0192 /*
0193  * 32bit TIMER1 to keep counting monotonically and wraparound
0194  */
0195
0196 static u64 arc_read_timer1(struct clocksource *cs)
0197 {
0198     return (u64) read_aux_reg(ARC_REG_TIMER1_CNT);
0199 }
0200
0201 static notrace u64 arc_timer1_clock_read(void)
0202 {
0203     return arc_read_timer1(NULL);
0204 }
0205
0206 static struct clocksource arc_counter_timer1 = {
0207     .name   = "ARC Timer1",
0208     .rating = 300,
0209     .read   = arc_read_timer1,
0210     .mask   = CLOCKSOURCE_MASK(32),
0211     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0212 };
0213
0214 static int __init arc_cs_setup_timer1(struct device_node *node)
0215 {
0216     int ret;
0217
0218     /* Local to CPU hence not usable in SMP */
0219     if (IS_ENABLED(CONFIG_SMP))
0220         return -EINVAL;
0221
0222     ret = arc_get_timer_clk(node);
0223     if (ret)
0224         return ret;
0225
0226     write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMERN_MAX);
0227     write_aux_reg(ARC_REG_TIMER1_CNT, 0);
0228     write_aux_reg(ARC_REG_TIMER1_CTRL, ARC_TIMER_CTRL_NH);
0229
0230     sched_clock_register(arc_timer1_clock_read, 32, arc_timer_freq);
0231
0232     return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);
0233 }
0234
0235 /********** Clock Event Device *********/
0236
0237 static int arc_timer_irq;
0238
0239 /*
0240  * Arm the timer to interrupt after @cycles
0241  * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
0242  */
0243 static void arc_timer_event_setup(unsigned int cycles)
0244 {
0245     write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
0246     write_aux_reg(ARC_REG_TIMER0_CNT, 0);   /* start from 0 */
0247
0248     write_aux_reg(ARC_REG_TIMER0_CTRL, ARC_TIMER_CTRL_IE | ARC_TIMER_CTRL_NH);
0249 }
0250
0251
0252 static int arc_clkevent_set_next_event(unsigned long delta,
0253                        struct clock_event_device *dev)
0254 {
0255     arc_timer_event_setup(delta);
0256     return 0;
0257 }
0258
0259 static int arc_clkevent_set_periodic(struct clock_event_device *dev)
0260 {
0261     /*
0262      * At X Hz, 1 sec = 1000ms -> X cycles;
0263      *            10ms -> X / 100 cycles
0264      */
0265     arc_timer_event_setup(arc_timer_freq / HZ);
0266     return 0;
0267 }
0268
0269 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
0270     .name           = "ARC Timer0",
0271     .features       = CLOCK_EVT_FEAT_ONESHOT |
0272                   CLOCK_EVT_FEAT_PERIODIC,
0273     .rating         = 300,
0274     .set_next_event     = arc_clkevent_set_next_event,
0275     .set_state_periodic = arc_clkevent_set_periodic,
0276 };
0277
0278 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
0279 {
0280     /*
0281      * Note that generic IRQ core could have passed @evt for @dev_id if
0282      * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
0283      */
0284     struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
0285     int irq_reenable = clockevent_state_periodic(evt);
0286
0287     /*
0288      * 1. ACK the interrupt
0289      *    - For ARC700, any write to CTRL reg ACKs it, so just rewrite
0290      *      Count when [N]ot [H]alted bit.
0291      *    - For HS3x, it is a bit subtle. On taken count-down interrupt,
0292      *      IP bit [3] is set, which needs to be cleared for ACK'ing.
0293      *      The write below can only update the other two bits, hence
0294      *      explicitly clears IP bit
0295      * 2. Re-arm interrupt if periodic by writing to IE bit [0]
0296      */
0297     write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | ARC_TIMER_CTRL_NH);
0298
0299     evt->event_handler(evt);
0300
0301     return IRQ_HANDLED;
0302 }
0303
0304
0305 static int arc_timer_starting_cpu(unsigned int cpu)
0306 {
0307     struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
0308
0309     evt->cpumask = cpumask_of(smp_processor_id());
0310
0311     clockevents_config_and_register(evt, arc_timer_freq, 0, ARC_TIMERN_MAX);
0312     enable_percpu_irq(arc_timer_irq, 0);
0313     return 0;
0314 }
0315
0316 static int arc_timer_dying_cpu(unsigned int cpu)
0317 {
0318     disable_percpu_irq(arc_timer_irq);
0319     return 0;
0320 }
0321
0322 /*
0323  * clockevent setup for boot CPU
0324  */
0325 static int __init arc_clockevent_setup(struct device_node *node)
0326 {
0327     struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
0328     int ret;
0329
0330     arc_timer_irq = irq_of_parse_and_map(node, 0);
0331     if (arc_timer_irq <= 0) {
0332         pr_err("clockevent: missing irq\n");
0333         return -EINVAL;
0334     }
0335
0336     ret = arc_get_timer_clk(node);
0337     if (ret)
0338         return ret;
0339
0340     /* Needs apriori irq_set_percpu_devid() done in intc map function */
0341     ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,
0342                  "Timer0 (per-cpu-tick)", evt);
0343     if (ret) {
0344         pr_err("clockevent: unable to request irq\n");
0345         return ret;
0346     }
0347
0348     ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING,
0349                 "clockevents/arc/timer:starting",
0350                 arc_timer_starting_cpu,
0351                 arc_timer_dying_cpu);
0352     if (ret) {
0353         pr_err("Failed to setup hotplug state\n");
0354         return ret;
0355     }
0356     return 0;
0357 }
0358
0359 static int __init arc_of_timer_init(struct device_node *np)
0360 {
0361     static int init_count = 0;
0362     int ret;
0363
0364     if (!init_count) {
0365         init_count = 1;
0366         ret = arc_clockevent_setup(np);
0367     } else {
0368         ret = arc_cs_setup_timer1(np);
0369     }
0370
0371     return ret;
0372 }
0373 TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);