drivers/clocksource/acpi_pm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * linux/drivers/clocksource/acpi_pm.c
0004  *
0005  * This file contains the ACPI PM based clocksource.
0006  *
0007  * This code was largely moved from the i386 timer_pm.c file
0008  * which was (C) Dominik Brodowski <linux@brodo.de> 2003
0009  * and contained the following comments:
0010  *
0011  * Driver to use the Power Management Timer (PMTMR) available in some
0012  * southbridges as primary timing source for the Linux kernel.
0013  *
0014  * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
0015  * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
0016  */
0017
0018 #include <linux/acpi_pmtmr.h>
0019 #include <linux/clocksource.h>
0020 #include <linux/timex.h>
0021 #include <linux/errno.h>
0022 #include <linux/init.h>
0023 #include <linux/pci.h>
0024 #include <linux/delay.h>
0025 #include <asm/io.h>
0026
0027 /*
0028  * The I/O port the PMTMR resides at.
0029  * The location is detected during setup_arch(),
0030  * in arch/i386/kernel/acpi/boot.c
0031  */
0032 u32 pmtmr_ioport __read_mostly;
0033
0034 static inline u32 read_pmtmr(void)
0035 {
0036     /* mask the output to 24 bits */
0037     return inl(pmtmr_ioport) & ACPI_PM_MASK;
0038 }
0039
0040 u32 acpi_pm_read_verified(void)
0041 {
0042     u32 v1 = 0, v2 = 0, v3 = 0;
0043
0044     /*
0045      * It has been reported that because of various broken
0046      * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
0047      * source is not latched, you must read it multiple
0048      * times to ensure a safe value is read:
0049      */
0050     do {
0051         v1 = read_pmtmr();
0052         v2 = read_pmtmr();
0053         v3 = read_pmtmr();
0054     } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
0055               || (v3 > v1 && v3 < v2)));
0056
0057     return v2;
0058 }
0059
0060 static u64 acpi_pm_read(struct clocksource *cs)
0061 {
0062     return (u64)read_pmtmr();
0063 }
0064
0065 static struct clocksource clocksource_acpi_pm = {
0066     .name       = "acpi_pm",
0067     .rating     = 200,
0068     .read       = acpi_pm_read,
0069     .mask       = (u64)ACPI_PM_MASK,
0070     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0071 };
0072
0073
0074 #ifdef CONFIG_PCI
0075 static int acpi_pm_good;
0076 static int __init acpi_pm_good_setup(char *__str)
0077 {
0078     acpi_pm_good = 1;
0079     return 1;
0080 }
0081 __setup("acpi_pm_good", acpi_pm_good_setup);
0082
0083 static u64 acpi_pm_read_slow(struct clocksource *cs)
0084 {
0085     return (u64)acpi_pm_read_verified();
0086 }
0087
0088 static inline void acpi_pm_need_workaround(void)
0089 {
0090     clocksource_acpi_pm.read = acpi_pm_read_slow;
0091     clocksource_acpi_pm.rating = 120;
0092 }
0093
0094 /*
0095  * PIIX4 Errata:
0096  *
0097  * The power management timer may return improper results when read.
0098  * Although the timer value settles properly after incrementing,
0099  * while incrementing there is a 3 ns window every 69.8 ns where the
0100  * timer value is indeterminate (a 4.2% chance that the data will be
0101  * incorrect when read). As a result, the ACPI free running count up
0102  * timer specification is violated due to erroneous reads.
0103  */
0104 static void acpi_pm_check_blacklist(struct pci_dev *dev)
0105 {
0106     if (acpi_pm_good)
0107         return;
0108
0109     /* the bug has been fixed in PIIX4M */
0110     if (dev->revision < 3) {
0111         pr_warn("* Found PM-Timer Bug on the chipset. Due to workarounds for a bug,\n"
0112             "* this clock source is slow. Consider trying other clock sources\n");
0113
0114         acpi_pm_need_workaround();
0115     }
0116 }
0117 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
0118             acpi_pm_check_blacklist);
0119
0120 static void acpi_pm_check_graylist(struct pci_dev *dev)
0121 {
0122     if (acpi_pm_good)
0123         return;
0124
0125     pr_warn("* The chipset may have PM-Timer Bug. Due to workarounds for a bug,\n"
0126         "* this clock source is slow. If you are sure your timer does not have\n"
0127         "* this bug, please use \"acpi_pm_good\" to disable the workaround\n");
0128
0129     acpi_pm_need_workaround();
0130 }
0131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
0132             acpi_pm_check_graylist);
0133 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
0134             acpi_pm_check_graylist);
0135 #endif
0136
0137 #ifndef CONFIG_X86_64
0138 #include <asm/mach_timer.h>
0139 #define PMTMR_EXPECTED_RATE \
0140   ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (PIT_TICK_RATE>>10))
0141 /*
0142  * Some boards have the PMTMR running way too fast. We check
0143  * the PMTMR rate against PIT channel 2 to catch these cases.
0144  */
0145 static int verify_pmtmr_rate(void)
0146 {
0147     u64 value1, value2;
0148     unsigned long count, delta;
0149
0150     mach_prepare_counter();
0151     value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
0152     mach_countup(&count);
0153     value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
0154     delta = (value2 - value1) & ACPI_PM_MASK;
0155
0156     /* Check that the PMTMR delta is within 5% of what we expect */
0157     if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
0158         delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
0159         pr_info("PM-Timer running at invalid rate: %lu%% of normal - aborting.\n",
0160             100UL * delta / PMTMR_EXPECTED_RATE);
0161         return -1;
0162     }
0163
0164     return 0;
0165 }
0166 #else
0167 #define verify_pmtmr_rate() (0)
0168 #endif
0169
0170 /* Number of monotonicity checks to perform during initialization */
0171 #define ACPI_PM_MONOTONICITY_CHECKS 10
0172 /* Number of reads we try to get two different values */
0173 #define ACPI_PM_READ_CHECKS 10000
0174
0175 static int __init init_acpi_pm_clocksource(void)
0176 {
0177     u64 value1, value2;
0178     unsigned int i, j = 0;
0179
0180     if (!pmtmr_ioport)
0181         return -ENODEV;
0182
0183     /* "verify" this timing source: */
0184     for (j = 0; j < ACPI_PM_MONOTONICITY_CHECKS; j++) {
0185         udelay(100 * j);
0186         value1 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
0187         for (i = 0; i < ACPI_PM_READ_CHECKS; i++) {
0188             value2 = clocksource_acpi_pm.read(&clocksource_acpi_pm);
0189             if (value2 == value1)
0190                 continue;
0191             if (value2 > value1)
0192                 break;
0193             if ((value2 < value1) && ((value2) < 0xFFF))
0194                 break;
0195             pr_info("PM-Timer had inconsistent results: %#llx, %#llx - aborting.\n",
0196                 value1, value2);
0197             pmtmr_ioport = 0;
0198             return -EINVAL;
0199         }
0200         if (i == ACPI_PM_READ_CHECKS) {
0201             pr_info("PM-Timer failed consistency check  (%#llx) - aborting.\n",
0202                 value1);
0203             pmtmr_ioport = 0;
0204             return -ENODEV;
0205         }
0206     }
0207
0208     if (verify_pmtmr_rate() != 0){
0209         pmtmr_ioport = 0;
0210         return -ENODEV;
0211     }
0212
0213     return clocksource_register_hz(&clocksource_acpi_pm,
0214                         PMTMR_TICKS_PER_SEC);
0215 }
0216
0217 /* We use fs_initcall because we want the PCI fixups to have run
0218  * but we still need to load before device_initcall
0219  */
0220 fs_initcall(init_acpi_pm_clocksource);
0221
0222 /*
0223  * Allow an override of the IOPort. Stupid BIOSes do not tell us about
0224  * the PMTimer, but we might know where it is.
0225  */
0226 static int __init parse_pmtmr(char *arg)
0227 {
0228     unsigned int base;
0229     int ret;
0230
0231     ret = kstrtouint(arg, 16, &base);
0232     if (ret) {
0233         pr_warn("PMTMR: invalid 'pmtmr=' value: '%s'\n", arg);
0234         return 1;
0235     }
0236
0237     pr_info("PMTMR IOPort override: 0x%04x -> 0x%04x\n", pmtmr_ioport,
0238         base);
0239     pmtmr_ioport = base;
0240
0241     return 1;
0242 }
0243 __setup("pmtmr=", parse_pmtmr);