clk/zynqmp/clk-zynqmp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  Copyright (C) 2016-2018 Xilinx
0004  */
0005
0006 #ifndef __LINUX_CLK_ZYNQMP_H_
0007 #define __LINUX_CLK_ZYNQMP_H_
0008
0009 #include <linux/spinlock.h>
0010
0011 #include <linux/firmware/xlnx-zynqmp.h>
0012
0013 /* Common Flags */
0014 /* must be gated across rate change */
0015 #define ZYNQMP_CLK_SET_RATE_GATE    BIT(0)
0016 /* must be gated across re-parent */
0017 #define ZYNQMP_CLK_SET_PARENT_GATE  BIT(1)
0018 /* propagate rate change up one level */
0019 #define ZYNQMP_CLK_SET_RATE_PARENT  BIT(2)
0020 /* do not gate even if unused */
0021 #define ZYNQMP_CLK_IGNORE_UNUSED    BIT(3)
0022 /* don't re-parent on rate change */
0023 #define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7)
0024 /* do not gate, ever */
0025 #define ZYNQMP_CLK_IS_CRITICAL      BIT(11)
0026
0027 /* Type Flags for divider clock */
0028 #define ZYNQMP_CLK_DIVIDER_ONE_BASED        BIT(0)
0029 #define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO     BIT(1)
0030 #define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO       BIT(2)
0031 #define ZYNQMP_CLK_DIVIDER_HIWORD_MASK      BIT(3)
0032 #define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST    BIT(4)
0033 #define ZYNQMP_CLK_DIVIDER_READ_ONLY        BIT(5)
0034 #define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO      BIT(6)
0035
0036 /* Type Flags for mux clock */
0037 #define ZYNQMP_CLK_MUX_INDEX_ONE        BIT(0)
0038 #define ZYNQMP_CLK_MUX_INDEX_BIT        BIT(1)
0039 #define ZYNQMP_CLK_MUX_HIWORD_MASK      BIT(2)
0040 #define ZYNQMP_CLK_MUX_READ_ONLY        BIT(3)
0041 #define ZYNQMP_CLK_MUX_ROUND_CLOSEST        BIT(4)
0042 #define ZYNQMP_CLK_MUX_BIG_ENDIAN       BIT(5)
0043
0044 enum topology_type {
0045     TYPE_INVALID,
0046     TYPE_MUX,
0047     TYPE_PLL,
0048     TYPE_FIXEDFACTOR,
0049     TYPE_DIV1,
0050     TYPE_DIV2,
0051     TYPE_GATE,
0052 };
0053
0054 /**
0055  * struct clock_topology - Clock topology
0056  * @type:   Type of topology
0057  * @flag:   Topology flags
0058  * @type_flag:  Topology type specific flag
0059  * @custom_type_flag: Topology type specific custom flag
0060  */
0061 struct clock_topology {
0062     u32 type;
0063     u32 flag;
0064     u32 type_flag;
0065     u8 custom_type_flag;
0066 };
0067
0068 unsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag);
0069
0070 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
0071                        const char * const *parents,
0072                        u8 num_parents,
0073                        const struct clock_topology *nodes);
0074
0075 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
0076                     const char * const *parents,
0077                     u8 num_parents,
0078                     const struct clock_topology *nodes);
0079
0080 struct clk_hw *zynqmp_clk_register_divider(const char *name,
0081                        u32 clk_id,
0082                        const char * const *parents,
0083                        u8 num_parents,
0084                        const struct clock_topology *nodes);
0085
0086 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
0087                        const char * const *parents,
0088                        u8 num_parents,
0089                        const struct clock_topology *nodes);
0090
0091 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
0092                     u32 clk_id,
0093                     const char * const *parents,
0094                     u8 num_parents,
0095                     const struct clock_topology *nodes);
0096
0097 #endif