clk/zynqmp/clk-gate-zynqmp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Zynq UltraScale+ MPSoC clock controller
0004  *
0005  *  Copyright (C) 2016-2018 Xilinx
0006  *
0007  * Gated clock implementation
0008  */
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/slab.h>
0012 #include "clk-zynqmp.h"
0013
0014 /**
0015  * struct zynqmp_clk_gate - gating clock
0016  * @hw:     handle between common and hardware-specific interfaces
0017  * @flags:  hardware-specific flags
0018  * @clk_id: Id of clock
0019  */
0020 struct zynqmp_clk_gate {
0021     struct clk_hw hw;
0022     u8 flags;
0023     u32 clk_id;
0024 };
0025
0026 #define to_zynqmp_clk_gate(_hw) container_of(_hw, struct zynqmp_clk_gate, hw)
0027
0028 /**
0029  * zynqmp_clk_gate_enable() - Enable clock
0030  * @hw:     handle between common and hardware-specific interfaces
0031  *
0032  * Return: 0 on success else error code
0033  */
0034 static int zynqmp_clk_gate_enable(struct clk_hw *hw)
0035 {
0036     struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
0037     const char *clk_name = clk_hw_get_name(hw);
0038     u32 clk_id = gate->clk_id;
0039     int ret;
0040
0041     ret = zynqmp_pm_clock_enable(clk_id);
0042
0043     if (ret)
0044         pr_debug("%s() clock enable failed for %s (id %d), ret = %d\n",
0045              __func__, clk_name, clk_id, ret);
0046
0047     return ret;
0048 }
0049
0050 /*
0051  * zynqmp_clk_gate_disable() - Disable clock
0052  * @hw:     handle between common and hardware-specific interfaces
0053  */
0054 static void zynqmp_clk_gate_disable(struct clk_hw *hw)
0055 {
0056     struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
0057     const char *clk_name = clk_hw_get_name(hw);
0058     u32 clk_id = gate->clk_id;
0059     int ret;
0060
0061     ret = zynqmp_pm_clock_disable(clk_id);
0062
0063     if (ret)
0064         pr_debug("%s() clock disable failed for %s (id %d), ret = %d\n",
0065              __func__, clk_name, clk_id, ret);
0066 }
0067
0068 /**
0069  * zynqmp_clk_gate_is_enabled() - Check clock state
0070  * @hw:     handle between common and hardware-specific interfaces
0071  *
0072  * Return: 1 if enabled, 0 if disabled else error code
0073  */
0074 static int zynqmp_clk_gate_is_enabled(struct clk_hw *hw)
0075 {
0076     struct zynqmp_clk_gate *gate = to_zynqmp_clk_gate(hw);
0077     const char *clk_name = clk_hw_get_name(hw);
0078     u32 clk_id = gate->clk_id;
0079     int state, ret;
0080
0081     ret = zynqmp_pm_clock_getstate(clk_id, &state);
0082     if (ret) {
0083         pr_debug("%s() clock get state failed for %s, ret = %d\n",
0084              __func__, clk_name, ret);
0085         return -EIO;
0086     }
0087
0088     return state ? 1 : 0;
0089 }
0090
0091 static const struct clk_ops zynqmp_clk_gate_ops = {
0092     .enable = zynqmp_clk_gate_enable,
0093     .disable = zynqmp_clk_gate_disable,
0094     .is_enabled = zynqmp_clk_gate_is_enabled,
0095 };
0096
0097 /**
0098  * zynqmp_clk_register_gate() - Register a gate clock with the clock framework
0099  * @name:       Name of this clock
0100  * @clk_id:     Id of this clock
0101  * @parents:        Name of this clock's parents
0102  * @num_parents:    Number of parents
0103  * @nodes:      Clock topology node
0104  *
0105  * Return: clock hardware of the registered clock gate
0106  */
0107 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
0108                     const char * const *parents,
0109                     u8 num_parents,
0110                     const struct clock_topology *nodes)
0111 {
0112     struct zynqmp_clk_gate *gate;
0113     struct clk_hw *hw;
0114     int ret;
0115     struct clk_init_data init;
0116
0117     /* allocate the gate */
0118     gate = kzalloc(sizeof(*gate), GFP_KERNEL);
0119     if (!gate)
0120         return ERR_PTR(-ENOMEM);
0121
0122     init.name = name;
0123     init.ops = &zynqmp_clk_gate_ops;
0124
0125     init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);
0126
0127     init.parent_names = parents;
0128     init.num_parents = 1;
0129
0130     /* struct clk_gate assignments */
0131     gate->flags = nodes->type_flag;
0132     gate->hw.init = &init;
0133     gate->clk_id = clk_id;
0134
0135     hw = &gate->hw;
0136     ret = clk_hw_register(NULL, hw);
0137     if (ret) {
0138         kfree(gate);
0139         hw = ERR_PTR(ret);
0140     }
0141
0142     return hw;
0143 }