clk/zynq/pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Zynq PLL driver
0004  *
0005  *  Copyright (C) 2013 Xilinx
0006  *
0007  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
0008  */
0009 #include <linux/clk/zynq.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/slab.h>
0012 #include <linux/io.h>
0013
0014 /**
0015  * struct zynq_pll - pll clock
0016  * @hw:     Handle between common and hardware-specific interfaces
0017  * @pll_ctrl:   PLL control register
0018  * @pll_status: PLL status register
0019  * @lock:   Register lock
0020  * @lockbit:    Indicates the associated PLL_LOCKED bit in the PLL status
0021  *      register.
0022  */
0023 struct zynq_pll {
0024     struct clk_hw   hw;
0025     void __iomem    *pll_ctrl;
0026     void __iomem    *pll_status;
0027     spinlock_t  *lock;
0028     u8      lockbit;
0029 };
0030 #define to_zynq_pll(_hw)    container_of(_hw, struct zynq_pll, hw)
0031
0032 /* Register bitfield defines */
0033 #define PLLCTRL_FBDIV_MASK  0x7f000
0034 #define PLLCTRL_FBDIV_SHIFT 12
0035 #define PLLCTRL_BPQUAL_MASK (1 << 3)
0036 #define PLLCTRL_PWRDWN_MASK 2
0037 #define PLLCTRL_PWRDWN_SHIFT    1
0038 #define PLLCTRL_RESET_MASK  1
0039 #define PLLCTRL_RESET_SHIFT 0
0040
0041 #define PLL_FBDIV_MIN   13
0042 #define PLL_FBDIV_MAX   66
0043
0044 /**
0045  * zynq_pll_round_rate() - Round a clock frequency
0046  * @hw:     Handle between common and hardware-specific interfaces
0047  * @rate:   Desired clock frequency
0048  * @prate:  Clock frequency of parent clock
0049  * Return:  frequency closest to @rate the hardware can generate.
0050  */
0051 static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0052         unsigned long *prate)
0053 {
0054     u32 fbdiv;
0055
0056     fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
0057     if (fbdiv < PLL_FBDIV_MIN)
0058         fbdiv = PLL_FBDIV_MIN;
0059     else if (fbdiv > PLL_FBDIV_MAX)
0060         fbdiv = PLL_FBDIV_MAX;
0061
0062     return *prate * fbdiv;
0063 }
0064
0065 /**
0066  * zynq_pll_recalc_rate() - Recalculate clock frequency
0067  * @hw:         Handle between common and hardware-specific interfaces
0068  * @parent_rate:    Clock frequency of parent clock
0069  * Return:      current clock frequency.
0070  */
0071 static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
0072         unsigned long parent_rate)
0073 {
0074     struct zynq_pll *clk = to_zynq_pll(hw);
0075     u32 fbdiv;
0076
0077     /*
0078      * makes probably sense to redundantly save fbdiv in the struct
0079      * zynq_pll to save the IO access.
0080      */
0081     fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
0082             PLLCTRL_FBDIV_SHIFT;
0083
0084     return parent_rate * fbdiv;
0085 }
0086
0087 /**
0088  * zynq_pll_is_enabled - Check if a clock is enabled
0089  * @hw:     Handle between common and hardware-specific interfaces
0090  * Return:  1 if the clock is enabled, 0 otherwise.
0091  *
0092  * Not sure this is a good idea, but since disabled means bypassed for
0093  * this clock implementation we say we are always enabled.
0094  */
0095 static int zynq_pll_is_enabled(struct clk_hw *hw)
0096 {
0097     unsigned long flags = 0;
0098     u32 reg;
0099     struct zynq_pll *clk = to_zynq_pll(hw);
0100
0101     spin_lock_irqsave(clk->lock, flags);
0102
0103     reg = readl(clk->pll_ctrl);
0104
0105     spin_unlock_irqrestore(clk->lock, flags);
0106
0107     return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
0108 }
0109
0110 /**
0111  * zynq_pll_enable - Enable clock
0112  * @hw:     Handle between common and hardware-specific interfaces
0113  * Return: 0 on success
0114  */
0115 static int zynq_pll_enable(struct clk_hw *hw)
0116 {
0117     unsigned long flags = 0;
0118     u32 reg;
0119     struct zynq_pll *clk = to_zynq_pll(hw);
0120
0121     if (zynq_pll_is_enabled(hw))
0122         return 0;
0123
0124     pr_info("PLL: enable\n");
0125
0126     /* Power up PLL and wait for lock */
0127     spin_lock_irqsave(clk->lock, flags);
0128
0129     reg = readl(clk->pll_ctrl);
0130     reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
0131     writel(reg, clk->pll_ctrl);
0132     while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
0133         ;
0134
0135     spin_unlock_irqrestore(clk->lock, flags);
0136
0137     return 0;
0138 }
0139
0140 /**
0141  * zynq_pll_disable - Disable clock
0142  * @hw:     Handle between common and hardware-specific interfaces
0143  * Returns 0 on success
0144  */
0145 static void zynq_pll_disable(struct clk_hw *hw)
0146 {
0147     unsigned long flags = 0;
0148     u32 reg;
0149     struct zynq_pll *clk = to_zynq_pll(hw);
0150
0151     if (!zynq_pll_is_enabled(hw))
0152         return;
0153
0154     pr_info("PLL: shutdown\n");
0155
0156     /* shut down PLL */
0157     spin_lock_irqsave(clk->lock, flags);
0158
0159     reg = readl(clk->pll_ctrl);
0160     reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
0161     writel(reg, clk->pll_ctrl);
0162
0163     spin_unlock_irqrestore(clk->lock, flags);
0164 }
0165
0166 static const struct clk_ops zynq_pll_ops = {
0167     .enable = zynq_pll_enable,
0168     .disable = zynq_pll_disable,
0169     .is_enabled = zynq_pll_is_enabled,
0170     .round_rate = zynq_pll_round_rate,
0171     .recalc_rate = zynq_pll_recalc_rate
0172 };
0173
0174 /**
0175  * clk_register_zynq_pll() - Register PLL with the clock framework
0176  * @name:   PLL name
0177  * @parent: Parent clock name
0178  * @pll_ctrl:   Pointer to PLL control register
0179  * @pll_status: Pointer to PLL status register
0180  * @lock_index: Bit index to this PLL's lock status bit in @pll_status
0181  * @lock:   Register lock
0182  * Return:  handle to the registered clock.
0183  */
0184 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
0185         void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
0186         spinlock_t *lock)
0187 {
0188     struct zynq_pll *pll;
0189     struct clk *clk;
0190     u32 reg;
0191     const char *parent_arr[1] = {parent};
0192     unsigned long flags = 0;
0193     struct clk_init_data initd = {
0194         .name = name,
0195         .parent_names = parent_arr,
0196         .ops = &zynq_pll_ops,
0197         .num_parents = 1,
0198         .flags = 0
0199     };
0200
0201     pll = kmalloc(sizeof(*pll), GFP_KERNEL);
0202     if (!pll)
0203         return ERR_PTR(-ENOMEM);
0204
0205     /* Populate the struct */
0206     pll->hw.init = &initd;
0207     pll->pll_ctrl = pll_ctrl;
0208     pll->pll_status = pll_status;
0209     pll->lockbit = lock_index;
0210     pll->lock = lock;
0211
0212     spin_lock_irqsave(pll->lock, flags);
0213
0214     reg = readl(pll->pll_ctrl);
0215     reg &= ~PLLCTRL_BPQUAL_MASK;
0216     writel(reg, pll->pll_ctrl);
0217
0218     spin_unlock_irqrestore(pll->lock, flags);
0219
0220     clk = clk_register(NULL, &pll->hw);
0221     if (WARN_ON(IS_ERR(clk)))
0222         goto free_pll;
0223
0224     return clk;
0225
0226 free_pll:
0227     kfree(pll);
0228
0229     return clk;
0230 }