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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Zynq clock controller
0004  *
0005  *  Copyright (C) 2012 - 2013 Xilinx
0006  *
0007  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
0008  */
0009 
0010 #include <linux/clk/zynq.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/slab.h>
0016 #include <linux/string.h>
0017 #include <linux/io.h>
0018 
0019 static void __iomem *zynq_clkc_base;
0020 
0021 #define SLCR_ARMPLL_CTRL        (zynq_clkc_base + 0x00)
0022 #define SLCR_DDRPLL_CTRL        (zynq_clkc_base + 0x04)
0023 #define SLCR_IOPLL_CTRL         (zynq_clkc_base + 0x08)
0024 #define SLCR_PLL_STATUS         (zynq_clkc_base + 0x0c)
0025 #define SLCR_ARM_CLK_CTRL       (zynq_clkc_base + 0x20)
0026 #define SLCR_DDR_CLK_CTRL       (zynq_clkc_base + 0x24)
0027 #define SLCR_DCI_CLK_CTRL       (zynq_clkc_base + 0x28)
0028 #define SLCR_APER_CLK_CTRL      (zynq_clkc_base + 0x2c)
0029 #define SLCR_GEM0_CLK_CTRL      (zynq_clkc_base + 0x40)
0030 #define SLCR_GEM1_CLK_CTRL      (zynq_clkc_base + 0x44)
0031 #define SLCR_SMC_CLK_CTRL       (zynq_clkc_base + 0x48)
0032 #define SLCR_LQSPI_CLK_CTRL     (zynq_clkc_base + 0x4c)
0033 #define SLCR_SDIO_CLK_CTRL      (zynq_clkc_base + 0x50)
0034 #define SLCR_UART_CLK_CTRL      (zynq_clkc_base + 0x54)
0035 #define SLCR_SPI_CLK_CTRL       (zynq_clkc_base + 0x58)
0036 #define SLCR_CAN_CLK_CTRL       (zynq_clkc_base + 0x5c)
0037 #define SLCR_CAN_MIOCLK_CTRL        (zynq_clkc_base + 0x60)
0038 #define SLCR_DBG_CLK_CTRL       (zynq_clkc_base + 0x64)
0039 #define SLCR_PCAP_CLK_CTRL      (zynq_clkc_base + 0x68)
0040 #define SLCR_FPGA0_CLK_CTRL     (zynq_clkc_base + 0x70)
0041 #define SLCR_621_TRUE           (zynq_clkc_base + 0xc4)
0042 #define SLCR_SWDT_CLK_SEL       (zynq_clkc_base + 0x204)
0043 
0044 #define NUM_MIO_PINS    54
0045 
0046 #define DBG_CLK_CTRL_CLKACT_TRC     BIT(0)
0047 #define DBG_CLK_CTRL_CPU_1XCLKACT   BIT(1)
0048 
0049 enum zynq_clk {
0050     armpll, ddrpll, iopll,
0051     cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
0052     ddr2x, ddr3x, dci,
0053     lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
0054     sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
0055     usb0_aper, usb1_aper, gem0_aper, gem1_aper,
0056     sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
0057     i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
0058     smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
0059 
0060 static struct clk *ps_clk;
0061 static struct clk *clks[clk_max];
0062 static struct clk_onecell_data clk_data;
0063 
0064 static DEFINE_SPINLOCK(armpll_lock);
0065 static DEFINE_SPINLOCK(ddrpll_lock);
0066 static DEFINE_SPINLOCK(iopll_lock);
0067 static DEFINE_SPINLOCK(armclk_lock);
0068 static DEFINE_SPINLOCK(swdtclk_lock);
0069 static DEFINE_SPINLOCK(ddrclk_lock);
0070 static DEFINE_SPINLOCK(dciclk_lock);
0071 static DEFINE_SPINLOCK(gem0clk_lock);
0072 static DEFINE_SPINLOCK(gem1clk_lock);
0073 static DEFINE_SPINLOCK(canclk_lock);
0074 static DEFINE_SPINLOCK(canmioclk_lock);
0075 static DEFINE_SPINLOCK(dbgclk_lock);
0076 static DEFINE_SPINLOCK(aperclk_lock);
0077 
0078 static const char *const armpll_parents[] __initconst = {"armpll_int",
0079     "ps_clk"};
0080 static const char *const ddrpll_parents[] __initconst = {"ddrpll_int",
0081     "ps_clk"};
0082 static const char *const iopll_parents[] __initconst = {"iopll_int",
0083     "ps_clk"};
0084 static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"};
0085 static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"};
0086 static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate",
0087     "can0_mio_mux"};
0088 static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate",
0089     "can1_mio_mux"};
0090 static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
0091     "dummy_name"};
0092 
0093 static const char *const dbgtrc_emio_input_names[] __initconst = {
0094     "trace_emio_clk"};
0095 static const char *const gem0_emio_input_names[] __initconst = {
0096     "gem0_emio_clk"};
0097 static const char *const gem1_emio_input_names[] __initconst = {
0098     "gem1_emio_clk"};
0099 static const char *const swdt_ext_clk_input_names[] __initconst = {
0100     "swdt_ext_clk"};
0101 
0102 static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
0103         const char *clk_name, void __iomem *fclk_ctrl_reg,
0104         const char **parents, int enable)
0105 {
0106     u32 enable_reg;
0107     char *mux_name;
0108     char *div0_name;
0109     char *div1_name;
0110     spinlock_t *fclk_lock;
0111     spinlock_t *fclk_gate_lock;
0112     void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
0113 
0114     fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
0115     if (!fclk_lock)
0116         goto err;
0117     fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
0118     if (!fclk_gate_lock)
0119         goto err_fclk_gate_lock;
0120     spin_lock_init(fclk_lock);
0121     spin_lock_init(fclk_gate_lock);
0122 
0123     mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
0124     if (!mux_name)
0125         goto err_mux_name;
0126     div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
0127     if (!div0_name)
0128         goto err_div0_name;
0129     div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
0130     if (!div1_name)
0131         goto err_div1_name;
0132 
0133     clk_register_mux(NULL, mux_name, parents, 4,
0134             CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
0135             fclk_lock);
0136 
0137     clk_register_divider(NULL, div0_name, mux_name,
0138             0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
0139             CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
0140 
0141     clk_register_divider(NULL, div1_name, div0_name,
0142             CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
0143             CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
0144             fclk_lock);
0145 
0146     clks[fclk] = clk_register_gate(NULL, clk_name,
0147             div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
0148             0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
0149     enable_reg = readl(fclk_gate_reg) & 1;
0150     if (enable && !enable_reg) {
0151         if (clk_prepare_enable(clks[fclk]))
0152             pr_warn("%s: FCLK%u enable failed\n", __func__,
0153                     fclk - fclk0);
0154     }
0155     kfree(mux_name);
0156     kfree(div0_name);
0157     kfree(div1_name);
0158 
0159     return;
0160 
0161 err_div1_name:
0162     kfree(div0_name);
0163 err_div0_name:
0164     kfree(mux_name);
0165 err_mux_name:
0166     kfree(fclk_gate_lock);
0167 err_fclk_gate_lock:
0168     kfree(fclk_lock);
0169 err:
0170     clks[fclk] = ERR_PTR(-ENOMEM);
0171 }
0172 
0173 static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
0174         enum zynq_clk clk1, const char *clk_name0,
0175         const char *clk_name1, void __iomem *clk_ctrl,
0176         const char **parents, unsigned int two_gates)
0177 {
0178     char *mux_name;
0179     char *div_name;
0180     spinlock_t *lock;
0181 
0182     lock = kmalloc(sizeof(*lock), GFP_KERNEL);
0183     if (!lock)
0184         goto err;
0185     spin_lock_init(lock);
0186 
0187     mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
0188     div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
0189 
0190     clk_register_mux(NULL, mux_name, parents, 4,
0191             CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
0192 
0193     clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
0194             CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
0195 
0196     clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
0197             CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
0198     if (two_gates)
0199         clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
0200                 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
0201 
0202     kfree(mux_name);
0203     kfree(div_name);
0204 
0205     return;
0206 
0207 err:
0208     clks[clk0] = ERR_PTR(-ENOMEM);
0209     if (two_gates)
0210         clks[clk1] = ERR_PTR(-ENOMEM);
0211 }
0212 
0213 static void __init zynq_clk_setup(struct device_node *np)
0214 {
0215     int i;
0216     u32 tmp;
0217     int ret;
0218     char *clk_name;
0219     unsigned int fclk_enable = 0;
0220     const char *clk_output_name[clk_max];
0221     const char *cpu_parents[4];
0222     const char *periph_parents[4];
0223     const char *swdt_ext_clk_mux_parents[2];
0224     const char *can_mio_mux_parents[NUM_MIO_PINS];
0225     const char *dummy_nm = "dummy_name";
0226 
0227     pr_info("Zynq clock init\n");
0228 
0229     /* get clock output names from DT */
0230     for (i = 0; i < clk_max; i++) {
0231         if (of_property_read_string_index(np, "clock-output-names",
0232                   i, &clk_output_name[i])) {
0233             pr_err("%s: clock output name not in DT\n", __func__);
0234             BUG();
0235         }
0236     }
0237     cpu_parents[0] = clk_output_name[armpll];
0238     cpu_parents[1] = clk_output_name[armpll];
0239     cpu_parents[2] = clk_output_name[ddrpll];
0240     cpu_parents[3] = clk_output_name[iopll];
0241     periph_parents[0] = clk_output_name[iopll];
0242     periph_parents[1] = clk_output_name[iopll];
0243     periph_parents[2] = clk_output_name[armpll];
0244     periph_parents[3] = clk_output_name[ddrpll];
0245 
0246     of_property_read_u32(np, "fclk-enable", &fclk_enable);
0247 
0248     /* ps_clk */
0249     ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
0250     if (ret) {
0251         pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
0252         tmp = 33333333;
0253     }
0254     ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
0255 
0256     /* PLLs */
0257     clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
0258             SLCR_PLL_STATUS, 0, &armpll_lock);
0259     clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
0260             armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
0261             SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
0262 
0263     clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
0264             SLCR_PLL_STATUS, 1, &ddrpll_lock);
0265     clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
0266             ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
0267             SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
0268 
0269     clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
0270             SLCR_PLL_STATUS, 2, &iopll_lock);
0271     clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
0272             iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
0273             SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
0274 
0275     /* CPU clocks */
0276     tmp = readl(SLCR_621_TRUE) & 1;
0277     clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
0278             CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
0279             &armclk_lock);
0280     clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
0281             SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
0282             CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
0283 
0284     clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
0285             "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
0286             SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
0287 
0288     clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
0289             1, 2);
0290     clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
0291             "cpu_3or2x_div", CLK_IGNORE_UNUSED,
0292             SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
0293 
0294     clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
0295             2 + tmp);
0296     clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
0297             "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
0298             26, 0, &armclk_lock);
0299     clk_prepare_enable(clks[cpu_2x]);
0300 
0301     clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
0302             4 + 2 * tmp);
0303     clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
0304             "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
0305             0, &armclk_lock);
0306 
0307     /* Timers */
0308     swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
0309     for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
0310         int idx = of_property_match_string(np, "clock-names",
0311                 swdt_ext_clk_input_names[i]);
0312         if (idx >= 0)
0313             swdt_ext_clk_mux_parents[i + 1] =
0314                 of_clk_get_parent_name(np, idx);
0315         else
0316             swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
0317     }
0318     clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
0319             swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
0320             CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
0321             &swdtclk_lock);
0322 
0323     /* DDR clocks */
0324     clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
0325             SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
0326             CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
0327     clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
0328             "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
0329     clk_prepare_enable(clks[ddr2x]);
0330     clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
0331             SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
0332             CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
0333     clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
0334             "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
0335     clk_prepare_enable(clks[ddr3x]);
0336 
0337     clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
0338             SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
0339             CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
0340     clk_register_divider(NULL, "dci_div1", "dci_div0",
0341             CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
0342             CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
0343             &dciclk_lock);
0344     clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
0345             CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
0346             &dciclk_lock);
0347     clk_prepare_enable(clks[dci]);
0348 
0349     /* Peripheral clocks */
0350     for (i = fclk0; i <= fclk3; i++) {
0351         int enable = !!(fclk_enable & BIT(i - fclk0));
0352 
0353         zynq_clk_register_fclk(i, clk_output_name[i],
0354                 SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
0355                 periph_parents, enable);
0356     }
0357 
0358     zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL,
0359                      SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
0360 
0361     zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL,
0362                      SLCR_SMC_CLK_CTRL, periph_parents, 0);
0363 
0364     zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL,
0365                      SLCR_PCAP_CLK_CTRL, periph_parents, 0);
0366 
0367     zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
0368             clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
0369             periph_parents, 1);
0370 
0371     zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
0372             clk_output_name[uart1], SLCR_UART_CLK_CTRL,
0373             periph_parents, 1);
0374 
0375     zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
0376             clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
0377             periph_parents, 1);
0378 
0379     for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
0380         int idx = of_property_match_string(np, "clock-names",
0381                 gem0_emio_input_names[i]);
0382         if (idx >= 0)
0383             gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
0384                     idx);
0385     }
0386     clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
0387             CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
0388             &gem0clk_lock);
0389     clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
0390             SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
0391             CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
0392     clk_register_divider(NULL, "gem0_div1", "gem0_div0",
0393             CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
0394             CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
0395             &gem0clk_lock);
0396     clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
0397             CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0398             SLCR_GEM0_CLK_CTRL, 6, 1, 0,
0399             &gem0clk_lock);
0400     clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
0401             "gem0_emio_mux", CLK_SET_RATE_PARENT,
0402             SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
0403 
0404     for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
0405         int idx = of_property_match_string(np, "clock-names",
0406                 gem1_emio_input_names[i]);
0407         if (idx >= 0)
0408             gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
0409                     idx);
0410     }
0411     clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
0412             CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
0413             &gem1clk_lock);
0414     clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
0415             SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
0416             CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
0417     clk_register_divider(NULL, "gem1_div1", "gem1_div0",
0418             CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
0419             CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
0420             &gem1clk_lock);
0421     clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
0422             CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
0423             SLCR_GEM1_CLK_CTRL, 6, 1, 0,
0424             &gem1clk_lock);
0425     clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
0426             "gem1_emio_mux", CLK_SET_RATE_PARENT,
0427             SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
0428 
0429     tmp = strlen("mio_clk_00x");
0430     clk_name = kmalloc(tmp, GFP_KERNEL);
0431     for (i = 0; i < NUM_MIO_PINS; i++) {
0432         int idx;
0433 
0434         snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
0435         idx = of_property_match_string(np, "clock-names", clk_name);
0436         if (idx >= 0)
0437             can_mio_mux_parents[i] = of_clk_get_parent_name(np,
0438                         idx);
0439         else
0440             can_mio_mux_parents[i] = dummy_nm;
0441     }
0442     kfree(clk_name);
0443     clk_register_mux(NULL, "can_mux", periph_parents, 4,
0444             CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
0445             &canclk_lock);
0446     clk_register_divider(NULL, "can_div0", "can_mux", 0,
0447             SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
0448             CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
0449     clk_register_divider(NULL, "can_div1", "can_div0",
0450             CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
0451             CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
0452             &canclk_lock);
0453     clk_register_gate(NULL, "can0_gate", "can_div1",
0454             CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
0455             &canclk_lock);
0456     clk_register_gate(NULL, "can1_gate", "can_div1",
0457             CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
0458             &canclk_lock);
0459     clk_register_mux(NULL, "can0_mio_mux",
0460             can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
0461             CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
0462             &canmioclk_lock);
0463     clk_register_mux(NULL, "can1_mio_mux",
0464             can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
0465             CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
0466             0, &canmioclk_lock);
0467     clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
0468             can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
0469             CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
0470             &canmioclk_lock);
0471     clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
0472             can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
0473             CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
0474             0, &canmioclk_lock);
0475 
0476     for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
0477         int idx = of_property_match_string(np, "clock-names",
0478                 dbgtrc_emio_input_names[i]);
0479         if (idx >= 0)
0480             dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
0481                     idx);
0482     }
0483     clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
0484             CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
0485             &dbgclk_lock);
0486     clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
0487             SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
0488             CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
0489     clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
0490             CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
0491             &dbgclk_lock);
0492     clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
0493             "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
0494             0, 0, &dbgclk_lock);
0495     clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
0496             clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
0497             &dbgclk_lock);
0498 
0499     /* leave debug clocks in the state the bootloader set them up to */
0500     tmp = readl(SLCR_DBG_CLK_CTRL);
0501     if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
0502         if (clk_prepare_enable(clks[dbg_trc]))
0503             pr_warn("%s: trace clk enable failed\n", __func__);
0504     if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT)
0505         if (clk_prepare_enable(clks[dbg_apb]))
0506             pr_warn("%s: debug APB clk enable failed\n", __func__);
0507 
0508     /* One gated clock for all APER clocks. */
0509     clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
0510             clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
0511             &aperclk_lock);
0512     clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
0513             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
0514             &aperclk_lock);
0515     clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
0516             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
0517             &aperclk_lock);
0518     clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
0519             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
0520             &aperclk_lock);
0521     clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
0522             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
0523             &aperclk_lock);
0524     clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
0525             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
0526             &aperclk_lock);
0527     clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
0528             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
0529             &aperclk_lock);
0530     clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
0531             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
0532             &aperclk_lock);
0533     clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
0534             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
0535             &aperclk_lock);
0536     clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
0537             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
0538             &aperclk_lock);
0539     clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
0540             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
0541             &aperclk_lock);
0542     clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
0543             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
0544             &aperclk_lock);
0545     clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
0546             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
0547             &aperclk_lock);
0548     clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
0549             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
0550             &aperclk_lock);
0551     clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
0552             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
0553             &aperclk_lock);
0554     clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
0555             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
0556             &aperclk_lock);
0557     clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
0558             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
0559             &aperclk_lock);
0560     clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
0561             clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
0562             &aperclk_lock);
0563 
0564     for (i = 0; i < ARRAY_SIZE(clks); i++) {
0565         if (IS_ERR(clks[i])) {
0566             pr_err("Zynq clk %d: register failed with %ld\n",
0567                    i, PTR_ERR(clks[i]));
0568             BUG();
0569         }
0570     }
0571 
0572     clk_data.clks = clks;
0573     clk_data.clk_num = ARRAY_SIZE(clks);
0574     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0575 }
0576 
0577 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
0578 
0579 void __init zynq_clock_init(void)
0580 {
0581     struct device_node *np;
0582     struct device_node *slcr;
0583     struct resource res;
0584 
0585     np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
0586     if (!np) {
0587         pr_err("%s: clkc node not found\n", __func__);
0588         goto np_err;
0589     }
0590 
0591     if (of_address_to_resource(np, 0, &res)) {
0592         pr_err("%pOFn: failed to get resource\n", np);
0593         goto np_err;
0594     }
0595 
0596     slcr = of_get_parent(np);
0597 
0598     if (slcr->data) {
0599         zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
0600     } else {
0601         pr_err("%pOFn: Unable to get I/O memory\n", np);
0602         of_node_put(slcr);
0603         goto np_err;
0604     }
0605 
0606     pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
0607 
0608     of_node_put(slcr);
0609     of_node_put(np);
0610 
0611     return;
0612 
0613 np_err:
0614     of_node_put(np);
0615     BUG();
0616 }
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