clk/x86/clk-lgm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020 Intel Corporation.
0004  * Zhu YiXin <yixin.zhu@intel.com>
0005  * Rahul Tanwar <rahul.tanwar@intel.com>
0006  */
0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 #include <linux/platform_device.h>
0010 #include <dt-bindings/clock/intel,lgm-clk.h>
0011 #include "clk-cgu.h"
0012
0013 #define PLL_DIV_WIDTH       4
0014 #define PLL_DDIV_WIDTH      3
0015
0016 /* Gate0 clock shift */
0017 #define G_C55_SHIFT     7
0018 #define G_QSPI_SHIFT        9
0019 #define G_EIP197_SHIFT      11
0020 #define G_VAULT130_SHIFT    12
0021 #define G_TOE_SHIFT     13
0022 #define G_SDXC_SHIFT        14
0023 #define G_EMMC_SHIFT        15
0024 #define G_SPIDBG_SHIFT      17
0025 #define G_DMA3_SHIFT        28
0026
0027 /* Gate1 clock shift */
0028 #define G_DMA0_SHIFT        0
0029 #define G_LEDC0_SHIFT       1
0030 #define G_LEDC1_SHIFT       2
0031 #define G_I2S0_SHIFT        3
0032 #define G_I2S1_SHIFT        4
0033 #define G_EBU_SHIFT     5
0034 #define G_PWM_SHIFT     6
0035 #define G_I2C0_SHIFT        7
0036 #define G_I2C1_SHIFT        8
0037 #define G_I2C2_SHIFT        9
0038 #define G_I2C3_SHIFT        10
0039
0040 #define G_SSC0_SHIFT        12
0041 #define G_SSC1_SHIFT        13
0042 #define G_SSC2_SHIFT        14
0043 #define G_SSC3_SHIFT        15
0044
0045 #define G_GPTC0_SHIFT       17
0046 #define G_GPTC1_SHIFT       18
0047 #define G_GPTC2_SHIFT       19
0048 #define G_GPTC3_SHIFT       20
0049
0050 #define G_ASC0_SHIFT        22
0051 #define G_ASC1_SHIFT        23
0052 #define G_ASC2_SHIFT        24
0053 #define G_ASC3_SHIFT        25
0054
0055 #define G_PCM0_SHIFT        27
0056 #define G_PCM1_SHIFT        28
0057 #define G_PCM2_SHIFT        29
0058
0059 /* Gate2 clock shift */
0060 #define G_PCIE10_SHIFT      1
0061 #define G_PCIE11_SHIFT      2
0062 #define G_PCIE30_SHIFT      3
0063 #define G_PCIE31_SHIFT      4
0064 #define G_PCIE20_SHIFT      5
0065 #define G_PCIE21_SHIFT      6
0066 #define G_PCIE40_SHIFT      7
0067 #define G_PCIE41_SHIFT      8
0068
0069 #define G_XPCS0_SHIFT       10
0070 #define G_XPCS1_SHIFT       11
0071 #define G_XPCS2_SHIFT       12
0072 #define G_XPCS3_SHIFT       13
0073 #define G_SATA0_SHIFT       14
0074 #define G_SATA1_SHIFT       15
0075 #define G_SATA2_SHIFT       16
0076 #define G_SATA3_SHIFT       17
0077
0078 /* Gate3 clock shift */
0079 #define G_ARCEM4_SHIFT      0
0080 #define G_IDMAR1_SHIFT      2
0081 #define G_IDMAT0_SHIFT      3
0082 #define G_IDMAT1_SHIFT      4
0083 #define G_IDMAT2_SHIFT      5
0084
0085 #define G_PPV4_SHIFT        8
0086 #define G_GSWIPO_SHIFT      9
0087 #define G_CQEM_SHIFT        10
0088 #define G_XPCS5_SHIFT       14
0089 #define G_USB1_SHIFT        25
0090 #define G_USB2_SHIFT        26
0091
0092
0093 /* Register definition */
0094 #define CGU_PLL0CZ_CFG0     0x000
0095 #define CGU_PLL0CM0_CFG0    0x020
0096 #define CGU_PLL0CM1_CFG0    0x040
0097 #define CGU_PLL0B_CFG0      0x060
0098 #define CGU_PLL1_CFG0       0x080
0099 #define CGU_PLL2_CFG0       0x0A0
0100 #define CGU_PLLPP_CFG0      0x0C0
0101 #define CGU_LJPLL3_CFG0     0x0E0
0102 #define CGU_LJPLL4_CFG0     0x100
0103 #define CGU_C55_PCMCR       0x18C
0104 #define CGU_PCMCR       0x190
0105 #define CGU_IF_CLK1     0x1A0
0106 #define CGU_IF_CLK2     0x1A4
0107 #define CGU_GATE0       0x300
0108 #define CGU_GATE1       0x310
0109 #define CGU_GATE2       0x320
0110 #define CGU_GATE3       0x310
0111
0112 #define PLL_DIV(x)      ((x) + 0x04)
0113 #define PLL_SSC(x)      ((x) + 0x10)
0114
0115 #define CLK_NR_CLKS     (LGM_GCLK_USB2 + 1)
0116
0117 /*
0118  * Below table defines the pair's of regval & effective dividers.
0119  * It's more efficient to provide an explicit table due to non-linear
0120  * relation between values.
0121  */
0122 static const struct clk_div_table pll_div[] = {
0123     { .val = 0, .div = 1 },
0124     { .val = 1, .div = 2 },
0125     { .val = 2, .div = 3 },
0126     { .val = 3, .div = 4 },
0127     { .val = 4, .div = 5 },
0128     { .val = 5, .div = 6 },
0129     { .val = 6, .div = 8 },
0130     { .val = 7, .div = 10 },
0131     { .val = 8, .div = 12 },
0132     { .val = 9, .div = 16 },
0133     { .val = 10, .div = 20 },
0134     { .val = 11, .div = 24 },
0135     { .val = 12, .div = 32 },
0136     { .val = 13, .div = 40 },
0137     { .val = 14, .div = 48 },
0138     { .val = 15, .div = 64 },
0139     {}
0140 };
0141
0142 static const struct clk_div_table dcl_div[] = {
0143     { .val = 0, .div = 6  },
0144     { .val = 1, .div = 12 },
0145     { .val = 2, .div = 24 },
0146     { .val = 3, .div = 32 },
0147     { .val = 4, .div = 48 },
0148     { .val = 5, .div = 96 },
0149     {}
0150 };
0151
0152 static const struct clk_parent_data pll_p[] = {
0153     { .fw_name = "osc", .name = "osc" },
0154 };
0155 static const struct clk_parent_data pllcm_p[] = {
0156     { .fw_name = "cpu_cm", .name = "cpu_cm" },
0157 };
0158 static const struct clk_parent_data emmc_p[] = {
0159     { .fw_name = "emmc4", .name = "emmc4" },
0160     { .fw_name = "noc4", .name = "noc4" },
0161 };
0162 static const struct clk_parent_data sdxc_p[] = {
0163     { .fw_name = "sdxc3", .name = "sdxc3" },
0164     { .fw_name = "sdxc2", .name = "sdxc2" },
0165 };
0166 static const struct clk_parent_data pcm_p[] = {
0167     { .fw_name = "v_docsis", .name = "v_docsis" },
0168     { .fw_name = "dcl", .name = "dcl" },
0169 };
0170 static const struct clk_parent_data cbphy_p[] = {
0171     { .fw_name = "dd_serdes", .name = "dd_serdes" },
0172     { .fw_name = "dd_pcie", .name = "dd_pcie" },
0173 };
0174
0175 static const struct lgm_pll_clk_data lgm_pll_clks[] = {
0176     LGM_PLL(LGM_CLK_PLL0CZ, "pll0cz", pll_p, CLK_IGNORE_UNUSED,
0177         CGU_PLL0CZ_CFG0, TYPE_ROPLL),
0178     LGM_PLL(LGM_CLK_PLL0CM0, "pll0cm0", pllcm_p, CLK_IGNORE_UNUSED,
0179         CGU_PLL0CM0_CFG0, TYPE_ROPLL),
0180     LGM_PLL(LGM_CLK_PLL0CM1, "pll0cm1", pllcm_p, CLK_IGNORE_UNUSED,
0181         CGU_PLL0CM1_CFG0, TYPE_ROPLL),
0182     LGM_PLL(LGM_CLK_PLL0B, "pll0b", pll_p, CLK_IGNORE_UNUSED,
0183         CGU_PLL0B_CFG0, TYPE_ROPLL),
0184     LGM_PLL(LGM_CLK_PLL1, "pll1", pll_p, 0, CGU_PLL1_CFG0, TYPE_ROPLL),
0185     LGM_PLL(LGM_CLK_PLL2, "pll2", pll_p, CLK_IGNORE_UNUSED,
0186         CGU_PLL2_CFG0, TYPE_ROPLL),
0187     LGM_PLL(LGM_CLK_PLLPP, "pllpp", pll_p, 0, CGU_PLLPP_CFG0, TYPE_ROPLL),
0188     LGM_PLL(LGM_CLK_LJPLL3, "ljpll3", pll_p, 0, CGU_LJPLL3_CFG0, TYPE_LJPLL),
0189     LGM_PLL(LGM_CLK_LJPLL4, "ljpll4", pll_p, 0, CGU_LJPLL4_CFG0, TYPE_LJPLL),
0190 };
0191
0192 static const struct lgm_clk_branch lgm_branch_clks[] = {
0193     LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
0194         0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
0195     LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
0196         4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
0197     LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
0198         8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
0199     LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
0200         12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
0201     LGM_DIV(LGM_CLK_DDR, "ddr", "pll2", CLK_IGNORE_UNUSED,
0202         PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
0203         pll_div),
0204     LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
0205         0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
0206
0207     LGM_DIV(LGM_CLK_IC, "cpu_ic", "pll0cz", CLK_IGNORE_UNUSED,
0208         PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
0209         1, 0, 0, pll_div),
0210
0211     LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
0212         8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
0213
0214     LGM_DIV(LGM_CLK_CPU0, "cm0", "pll0cm0",
0215         CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
0216         0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
0217     LGM_DIV(LGM_CLK_CPU1, "cm1", "pll0cm1",
0218         CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM1_CFG0),
0219         0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
0220
0221     /*
0222      * Marking ngi_clk (next generation interconnect) and noc_clk
0223      * (network on chip peripheral clk) as critical clocks because
0224      * these are shared parent clock sources for many different
0225      * peripherals.
0226      */
0227     LGM_DIV(LGM_CLK_NGI, "ngi", "pll0b",
0228         (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
0229         0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
0230     LGM_DIV(LGM_CLK_NOC4, "noc4", "pll0b",
0231         (CLK_IGNORE_UNUSED|CLK_IS_CRITICAL), PLL_DIV(CGU_PLL0B_CFG0),
0232         4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
0233     LGM_DIV(LGM_CLK_SW, "switch", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
0234         8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
0235     LGM_DIV(LGM_CLK_QSPI, "qspi", "pll0b", 0, PLL_DIV(CGU_PLL0B_CFG0),
0236         12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
0237     LGM_DIV(LGM_CLK_CT, "v_ct", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
0238         0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
0239     LGM_DIV(LGM_CLK_DSP, "v_dsp", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
0240         8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
0241     LGM_DIV(LGM_CLK_VIF, "v_ifclk", "pll1", 0, PLL_DIV(CGU_PLL1_CFG0),
0242         12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
0243
0244     LGM_FIXED_FACTOR(LGM_CLK_EMMC4, "emmc4", "sdxc3", 0,  0,
0245              0, 0, 0, 0, 1, 4),
0246     LGM_FIXED_FACTOR(LGM_CLK_SDXC2, "sdxc2", "noc4", 0,  0,
0247              0, 0, 0, 0, 1, 4),
0248     LGM_MUX(LGM_CLK_EMMC, "emmc", emmc_p, 0, CGU_IF_CLK1,
0249         0, 1, CLK_MUX_ROUND_CLOSEST, 0),
0250     LGM_MUX(LGM_CLK_SDXC, "sdxc", sdxc_p, 0, CGU_IF_CLK1,
0251         1, 1, CLK_MUX_ROUND_CLOSEST, 0),
0252     LGM_FIXED(LGM_CLK_OSC, "osc", NULL, 0, 0, 0, 0, 0, 40000000, 0),
0253     LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
0254           8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
0255     LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
0256     LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
0257         25, 3, 0, 0, 0, 0, dcl_div),
0258     LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
0259         0, 1, CLK_MUX_ROUND_CLOSEST, 0),
0260     LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",
0261              CLK_IGNORE_UNUSED, 0,
0262              0, 0, 0, 0, 2, 1),
0263     LGM_FIXED_FACTOR(LGM_CLK_PONDEF, "pondef", "dd_pool",
0264              CLK_SET_RATE_PARENT, 0, 0, 0, 0, 0, 1, 2),
0265     LGM_MUX(LGM_CLK_CBPHY0, "cbphy0", cbphy_p, 0, 0,
0266         0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
0267     LGM_MUX(LGM_CLK_CBPHY1, "cbphy1", cbphy_p, 0, 0,
0268         0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
0269     LGM_MUX(LGM_CLK_CBPHY2, "cbphy2", cbphy_p, 0, 0,
0270         0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
0271     LGM_MUX(LGM_CLK_CBPHY3, "cbphy3", cbphy_p, 0, 0,
0272         0, 0, MUX_CLK_SW | CLK_MUX_ROUND_CLOSEST, 0),
0273
0274     LGM_GATE(LGM_GCLK_C55, "g_c55", NULL, 0, CGU_GATE0,
0275          G_C55_SHIFT, 0, 0),
0276     LGM_GATE(LGM_GCLK_QSPI, "g_qspi", "qspi", 0, CGU_GATE0,
0277          G_QSPI_SHIFT, 0, 0),
0278     LGM_GATE(LGM_GCLK_EIP197, "g_eip197", NULL, 0, CGU_GATE0,
0279          G_EIP197_SHIFT, 0, 0),
0280     LGM_GATE(LGM_GCLK_VAULT, "g_vault130", NULL, 0, CGU_GATE0,
0281          G_VAULT130_SHIFT, 0, 0),
0282     LGM_GATE(LGM_GCLK_TOE, "g_toe", NULL, 0, CGU_GATE0,
0283          G_TOE_SHIFT, 0, 0),
0284     LGM_GATE(LGM_GCLK_SDXC, "g_sdxc", "sdxc", 0, CGU_GATE0,
0285          G_SDXC_SHIFT, 0, 0),
0286     LGM_GATE(LGM_GCLK_EMMC, "g_emmc", "emmc", 0, CGU_GATE0,
0287          G_EMMC_SHIFT, 0, 0),
0288     LGM_GATE(LGM_GCLK_SPI_DBG, "g_spidbg", NULL, 0, CGU_GATE0,
0289          G_SPIDBG_SHIFT, 0, 0),
0290     LGM_GATE(LGM_GCLK_DMA3, "g_dma3", NULL, 0, CGU_GATE0,
0291          G_DMA3_SHIFT, 0, 0),
0292
0293     LGM_GATE(LGM_GCLK_DMA0, "g_dma0", NULL, 0, CGU_GATE1,
0294          G_DMA0_SHIFT, 0, 0),
0295     LGM_GATE(LGM_GCLK_LEDC0, "g_ledc0", NULL, 0, CGU_GATE1,
0296          G_LEDC0_SHIFT, 0, 0),
0297     LGM_GATE(LGM_GCLK_LEDC1, "g_ledc1", NULL, 0, CGU_GATE1,
0298          G_LEDC1_SHIFT, 0, 0),
0299     LGM_GATE(LGM_GCLK_I2S0, "g_i2s0", NULL, 0, CGU_GATE1,
0300          G_I2S0_SHIFT, 0, 0),
0301     LGM_GATE(LGM_GCLK_I2S1, "g_i2s1", NULL, 0, CGU_GATE1,
0302          G_I2S1_SHIFT, 0, 0),
0303     LGM_GATE(LGM_GCLK_EBU, "g_ebu", NULL, 0, CGU_GATE1,
0304          G_EBU_SHIFT, 0, 0),
0305     LGM_GATE(LGM_GCLK_PWM, "g_pwm", NULL, 0, CGU_GATE1,
0306          G_PWM_SHIFT, 0, 0),
0307     LGM_GATE(LGM_GCLK_I2C0, "g_i2c0", NULL, 0, CGU_GATE1,
0308          G_I2C0_SHIFT, 0, 0),
0309     LGM_GATE(LGM_GCLK_I2C1, "g_i2c1", NULL, 0, CGU_GATE1,
0310          G_I2C1_SHIFT, 0, 0),
0311     LGM_GATE(LGM_GCLK_I2C2, "g_i2c2", NULL, 0, CGU_GATE1,
0312          G_I2C2_SHIFT, 0, 0),
0313     LGM_GATE(LGM_GCLK_I2C3, "g_i2c3", NULL, 0, CGU_GATE1,
0314          G_I2C3_SHIFT, 0, 0),
0315     LGM_GATE(LGM_GCLK_SSC0, "g_ssc0", "noc4", 0, CGU_GATE1,
0316          G_SSC0_SHIFT, 0, 0),
0317     LGM_GATE(LGM_GCLK_SSC1, "g_ssc1", "noc4", 0, CGU_GATE1,
0318          G_SSC1_SHIFT, 0, 0),
0319     LGM_GATE(LGM_GCLK_SSC2, "g_ssc2", "noc4", 0, CGU_GATE1,
0320          G_SSC2_SHIFT, 0, 0),
0321     LGM_GATE(LGM_GCLK_SSC3, "g_ssc3", "noc4", 0, CGU_GATE1,
0322          G_SSC3_SHIFT, 0, 0),
0323     LGM_GATE(LGM_GCLK_GPTC0, "g_gptc0", "noc4", 0, CGU_GATE1,
0324          G_GPTC0_SHIFT, 0, 0),
0325     LGM_GATE(LGM_GCLK_GPTC1, "g_gptc1", "noc4", 0, CGU_GATE1,
0326          G_GPTC1_SHIFT, 0, 0),
0327     LGM_GATE(LGM_GCLK_GPTC2, "g_gptc2", "noc4", 0, CGU_GATE1,
0328          G_GPTC2_SHIFT, 0, 0),
0329     LGM_GATE(LGM_GCLK_GPTC3, "g_gptc3", "osc", 0, CGU_GATE1,
0330          G_GPTC3_SHIFT, 0, 0),
0331     LGM_GATE(LGM_GCLK_ASC0, "g_asc0", "noc4", 0, CGU_GATE1,
0332          G_ASC0_SHIFT, 0, 0),
0333     LGM_GATE(LGM_GCLK_ASC1, "g_asc1", "noc4", 0, CGU_GATE1,
0334          G_ASC1_SHIFT, 0, 0),
0335     LGM_GATE(LGM_GCLK_ASC2, "g_asc2", "noc4", 0, CGU_GATE1,
0336          G_ASC2_SHIFT, 0, 0),
0337     LGM_GATE(LGM_GCLK_ASC3, "g_asc3", "osc", 0, CGU_GATE1,
0338          G_ASC3_SHIFT, 0, 0),
0339     LGM_GATE(LGM_GCLK_PCM0, "g_pcm0", NULL, 0, CGU_GATE1,
0340          G_PCM0_SHIFT, 0, 0),
0341     LGM_GATE(LGM_GCLK_PCM1, "g_pcm1", NULL, 0, CGU_GATE1,
0342          G_PCM1_SHIFT, 0, 0),
0343     LGM_GATE(LGM_GCLK_PCM2, "g_pcm2", NULL, 0, CGU_GATE1,
0344          G_PCM2_SHIFT, 0, 0),
0345
0346     LGM_GATE(LGM_GCLK_PCIE10, "g_pcie10", NULL, 0, CGU_GATE2,
0347          G_PCIE10_SHIFT, 0, 0),
0348     LGM_GATE(LGM_GCLK_PCIE11, "g_pcie11", NULL, 0, CGU_GATE2,
0349          G_PCIE11_SHIFT, 0, 0),
0350     LGM_GATE(LGM_GCLK_PCIE30, "g_pcie30", NULL, 0, CGU_GATE2,
0351          G_PCIE30_SHIFT, 0, 0),
0352     LGM_GATE(LGM_GCLK_PCIE31, "g_pcie31", NULL, 0, CGU_GATE2,
0353          G_PCIE31_SHIFT, 0, 0),
0354     LGM_GATE(LGM_GCLK_PCIE20, "g_pcie20", NULL, 0, CGU_GATE2,
0355          G_PCIE20_SHIFT, 0, 0),
0356     LGM_GATE(LGM_GCLK_PCIE21, "g_pcie21", NULL, 0, CGU_GATE2,
0357          G_PCIE21_SHIFT, 0, 0),
0358     LGM_GATE(LGM_GCLK_PCIE40, "g_pcie40", NULL, 0, CGU_GATE2,
0359          G_PCIE40_SHIFT, 0, 0),
0360     LGM_GATE(LGM_GCLK_PCIE41, "g_pcie41", NULL, 0, CGU_GATE2,
0361          G_PCIE41_SHIFT, 0, 0),
0362     LGM_GATE(LGM_GCLK_XPCS0, "g_xpcs0", NULL, 0, CGU_GATE2,
0363          G_XPCS0_SHIFT, 0, 0),
0364     LGM_GATE(LGM_GCLK_XPCS1, "g_xpcs1", NULL, 0, CGU_GATE2,
0365          G_XPCS1_SHIFT, 0, 0),
0366     LGM_GATE(LGM_GCLK_XPCS2, "g_xpcs2", NULL, 0, CGU_GATE2,
0367          G_XPCS2_SHIFT, 0, 0),
0368     LGM_GATE(LGM_GCLK_XPCS3, "g_xpcs3", NULL, 0, CGU_GATE2,
0369          G_XPCS3_SHIFT, 0, 0),
0370     LGM_GATE(LGM_GCLK_SATA0, "g_sata0", NULL, 0, CGU_GATE2,
0371          G_SATA0_SHIFT, 0, 0),
0372     LGM_GATE(LGM_GCLK_SATA1, "g_sata1", NULL, 0, CGU_GATE2,
0373          G_SATA1_SHIFT, 0, 0),
0374     LGM_GATE(LGM_GCLK_SATA2, "g_sata2", NULL, 0, CGU_GATE2,
0375          G_SATA2_SHIFT, 0, 0),
0376     LGM_GATE(LGM_GCLK_SATA3, "g_sata3", NULL, 0, CGU_GATE2,
0377          G_SATA3_SHIFT, 0, 0),
0378
0379     LGM_GATE(LGM_GCLK_ARCEM4, "g_arcem4", NULL, 0, CGU_GATE3,
0380          G_ARCEM4_SHIFT, 0, 0),
0381     LGM_GATE(LGM_GCLK_IDMAR1, "g_idmar1", NULL, 0, CGU_GATE3,
0382          G_IDMAR1_SHIFT, 0, 0),
0383     LGM_GATE(LGM_GCLK_IDMAT0, "g_idmat0", NULL, 0, CGU_GATE3,
0384          G_IDMAT0_SHIFT, 0, 0),
0385     LGM_GATE(LGM_GCLK_IDMAT1, "g_idmat1", NULL, 0, CGU_GATE3,
0386          G_IDMAT1_SHIFT, 0, 0),
0387     LGM_GATE(LGM_GCLK_IDMAT2, "g_idmat2", NULL, 0, CGU_GATE3,
0388          G_IDMAT2_SHIFT, 0, 0),
0389     LGM_GATE(LGM_GCLK_PPV4, "g_ppv4", NULL, 0, CGU_GATE3,
0390          G_PPV4_SHIFT, 0, 0),
0391     LGM_GATE(LGM_GCLK_GSWIPO, "g_gswipo", "switch", 0, CGU_GATE3,
0392          G_GSWIPO_SHIFT, 0, 0),
0393     LGM_GATE(LGM_GCLK_CQEM, "g_cqem", "switch", 0, CGU_GATE3,
0394          G_CQEM_SHIFT, 0, 0),
0395     LGM_GATE(LGM_GCLK_XPCS5, "g_xpcs5", NULL, 0, CGU_GATE3,
0396          G_XPCS5_SHIFT, 0, 0),
0397     LGM_GATE(LGM_GCLK_USB1, "g_usb1", NULL, 0, CGU_GATE3,
0398          G_USB1_SHIFT, 0, 0),
0399     LGM_GATE(LGM_GCLK_USB2, "g_usb2", NULL, 0, CGU_GATE3,
0400          G_USB2_SHIFT, 0, 0),
0401 };
0402
0403
0404 static const struct lgm_clk_ddiv_data lgm_ddiv_clks[] = {
0405     LGM_DDIV(LGM_CLK_CML, "dd_cml", "ljpll3", 0,
0406          PLL_DIV(CGU_LJPLL3_CFG0), 0, PLL_DDIV_WIDTH,
0407          3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
0408     LGM_DDIV(LGM_CLK_SERDES, "dd_serdes", "ljpll3", 0,
0409          PLL_DIV(CGU_LJPLL3_CFG0), 6, PLL_DDIV_WIDTH,
0410          9, PLL_DDIV_WIDTH, 25, 1, 28, 0),
0411     LGM_DDIV(LGM_CLK_POOL, "dd_pool", "ljpll3", 0,
0412          PLL_DIV(CGU_LJPLL3_CFG0), 12, PLL_DDIV_WIDTH,
0413          15, PLL_DDIV_WIDTH, 26, 1, 28, 0),
0414     LGM_DDIV(LGM_CLK_PTP, "dd_ptp", "ljpll3", 0,
0415          PLL_DIV(CGU_LJPLL3_CFG0), 18, PLL_DDIV_WIDTH,
0416          21, PLL_DDIV_WIDTH, 27, 1, 28, 0),
0417     LGM_DDIV(LGM_CLK_PCIE, "dd_pcie", "ljpll4", 0,
0418          PLL_DIV(CGU_LJPLL4_CFG0), 0, PLL_DDIV_WIDTH,
0419          3, PLL_DDIV_WIDTH, 24, 1, 29, 0),
0420 };
0421
0422 static int lgm_cgu_probe(struct platform_device *pdev)
0423 {
0424     struct lgm_clk_provider *ctx;
0425     struct device *dev = &pdev->dev;
0426     struct device_node *np = dev->of_node;
0427     int ret;
0428
0429     ctx = devm_kzalloc(dev, struct_size(ctx, clk_data.hws, CLK_NR_CLKS),
0430                GFP_KERNEL);
0431     if (!ctx)
0432         return -ENOMEM;
0433
0434     ctx->clk_data.num = CLK_NR_CLKS;
0435
0436     ctx->membase = devm_platform_ioremap_resource(pdev, 0);
0437     if (IS_ERR(ctx->membase))
0438         return PTR_ERR(ctx->membase);
0439
0440     ctx->np = np;
0441     ctx->dev = dev;
0442     spin_lock_init(&ctx->lock);
0443
0444     ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
0445                     ARRAY_SIZE(lgm_pll_clks));
0446     if (ret)
0447         return ret;
0448
0449     ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
0450                     ARRAY_SIZE(lgm_branch_clks));
0451     if (ret)
0452         return ret;
0453
0454     ret = lgm_clk_register_ddiv(ctx, lgm_ddiv_clks,
0455                     ARRAY_SIZE(lgm_ddiv_clks));
0456     if (ret)
0457         return ret;
0458
0459     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
0460                        &ctx->clk_data);
0461 }
0462
0463 static const struct of_device_id of_lgm_cgu_match[] = {
0464     { .compatible = "intel,cgu-lgm" },
0465     {}
0466 };
0467
0468 static struct platform_driver lgm_cgu_driver = {
0469     .probe = lgm_cgu_probe,
0470     .driver = {
0471            .name = "cgu-lgm",
0472            .of_match_table = of_lgm_cgu_match,
0473     },
0474 };
0475 builtin_platform_driver(lgm_cgu_driver);