clk/x86/clk-fch.c

0001 // SPDX-License-Identifier: MIT
0002 /*
0003  * clock framework for AMD FCH controller block
0004  *
0005  * Copyright 2018 Advanced Micro Devices, Inc.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/pci.h>
0012 #include <linux/platform_data/clk-fch.h>
0013 #include <linux/platform_device.h>
0014
0015 /* Clock Driving Strength 2 register */
0016 #define CLKDRVSTR2  0x28
0017 /* Clock Control 1 register */
0018 #define MISCCLKCNTL1    0x40
0019 /* Auxiliary clock1 enable bit */
0020 #define OSCCLKENB   2
0021 /* 25Mhz auxiliary output clock freq bit */
0022 #define OSCOUT1CLK25MHZ 16
0023
0024 #define ST_CLK_48M  0
0025 #define ST_CLK_25M  1
0026 #define ST_CLK_MUX  2
0027 #define ST_CLK_GATE 3
0028 #define ST_MAX_CLKS 4
0029
0030 #define CLK_48M_FIXED   0
0031 #define CLK_GATE_FIXED  1
0032 #define CLK_MAX_FIXED   2
0033
0034 /* List of supported CPU ids for clk mux with 25Mhz clk support */
0035 #define AMD_CPU_ID_ST                  0x1576
0036
0037 static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
0038 static struct clk_hw *hws[ST_MAX_CLKS];
0039
0040 static const struct pci_device_id fch_pci_ids[] = {
0041     { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_ST) },
0042     { }
0043 };
0044
0045 static int fch_clk_probe(struct platform_device *pdev)
0046 {
0047     struct fch_clk_data *fch_data;
0048     struct pci_dev *rdev;
0049
0050     fch_data = dev_get_platdata(&pdev->dev);
0051     if (!fch_data || !fch_data->base)
0052         return -EINVAL;
0053
0054     rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
0055     if (!rdev) {
0056         dev_err(&pdev->dev, "FCH device not found\n");
0057         return -ENODEV;
0058     }
0059
0060     if (pci_match_id(fch_pci_ids, rdev)) {
0061         hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
0062             NULL, 0, 48000000);
0063         hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
0064             NULL, 0, 25000000);
0065
0066         hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
0067             clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
0068             0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
0069             NULL);
0070
0071         clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
0072
0073         hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
0074             "oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,
0075             OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
0076
0077         devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
0078                         fch_data->name, NULL);
0079     } else {
0080         hws[CLK_48M_FIXED] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
0081             NULL, 0, 48000000);
0082
0083         hws[CLK_GATE_FIXED] = clk_hw_register_gate(NULL, "oscout1",
0084             "clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
0085             OSCCLKENB, 0, NULL);
0086
0087         devm_clk_hw_register_clkdev(&pdev->dev, hws[CLK_GATE_FIXED],
0088                         fch_data->name, NULL);
0089     }
0090
0091     pci_dev_put(rdev);
0092     return 0;
0093 }
0094
0095 static int fch_clk_remove(struct platform_device *pdev)
0096 {
0097     int i, clks;
0098     struct pci_dev *rdev;
0099
0100     rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
0101     if (!rdev)
0102         return -ENODEV;
0103
0104     clks = pci_match_id(fch_pci_ids, rdev) ? CLK_MAX_FIXED : ST_MAX_CLKS;
0105
0106     for (i = 0; i < clks; i++)
0107         clk_hw_unregister(hws[i]);
0108
0109     pci_dev_put(rdev);
0110     return 0;
0111 }
0112
0113 static struct platform_driver fch_clk_driver = {
0114     .driver = {
0115         .name = "clk-fch",
0116         .suppress_bind_attrs = true,
0117     },
0118     .probe = fch_clk_probe,
0119     .remove = fch_clk_remove,
0120 };
0121 builtin_platform_driver(fch_clk_driver);