clk/versatile/icst.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/arch/arm/common/icst307.c
0004  *
0005  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
0006  *
0007  *  Support functions for calculating clocks/divisors for the ICST307
0008  *  clock generators.  See https://www.idt.com/ for more information
0009  *  on these devices.
0010  *
0011  *  This is an almost identical implementation to the ICST525 clock generator.
0012  *  The s2div and idx2s files are different
0013  */
0014 #include <linux/module.h>
0015 #include <linux/kernel.h>
0016 #include <asm/div64.h>
0017 #include "icst.h"
0018
0019 /*
0020  * Divisors for each OD setting.
0021  */
0022 const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
0023 const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
0024 EXPORT_SYMBOL(icst307_s2div);
0025 EXPORT_SYMBOL(icst525_s2div);
0026
0027 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
0028 {
0029     u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
0030     u32 divisor = (vco.r + 2) * p->s2div[vco.s];
0031
0032     do_div(dividend, divisor);
0033     return (unsigned long)dividend;
0034 }
0035
0036 EXPORT_SYMBOL(icst_hz);
0037
0038 /*
0039  * Ascending divisor S values.
0040  */
0041 const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
0042 const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };
0043 EXPORT_SYMBOL(icst307_idx2s);
0044 EXPORT_SYMBOL(icst525_idx2s);
0045
0046 struct icst_vco
0047 icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
0048 {
0049     struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
0050     unsigned long f;
0051     unsigned int i = 0, rd, best = (unsigned int)-1;
0052
0053     /*
0054      * First, find the PLL output divisor such
0055      * that the PLL output is within spec.
0056      */
0057     do {
0058         f = freq * p->s2div[p->idx2s[i]];
0059
0060         if (f > p->vco_min && f <= p->vco_max)
0061             break;
0062         i++;
0063     } while (i < 8);
0064
0065     if (i >= 8)
0066         return vco;
0067
0068     vco.s = p->idx2s[i];
0069
0070     /*
0071      * Now find the closest divisor combination
0072      * which gives a PLL output of 'f'.
0073      */
0074     for (rd = p->rd_min; rd <= p->rd_max; rd++) {
0075         unsigned long fref_div, f_pll;
0076         unsigned int vd;
0077         int f_diff;
0078
0079         fref_div = (2 * p->ref) / rd;
0080
0081         vd = (f + fref_div / 2) / fref_div;
0082         if (vd < p->vd_min || vd > p->vd_max)
0083             continue;
0084
0085         f_pll = fref_div * vd;
0086         f_diff = f_pll - f;
0087         if (f_diff < 0)
0088             f_diff = -f_diff;
0089
0090         if ((unsigned)f_diff < best) {
0091             vco.v = vd - 8;
0092             vco.r = rd - 2;
0093             if (f_diff == 0)
0094                 break;
0095             best = f_diff;
0096         }
0097     }
0098
0099     return vco;
0100 }
0101
0102 EXPORT_SYMBOL(icst_hz_to_vco);