clk/ux500/u8500_of_clk.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Clock definitions for u8500 platform.
0004  *
0005  * Copyright (C) 2012 ST-Ericsson SA
0006  * Author: Ulf Hansson <ulf.hansson@linaro.org>
0007  */
0008
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/mfd/dbx500-prcmu.h>
0013
0014 #include "clk.h"
0015 #include "prcc.h"
0016 #include "reset-prcc.h"
0017
0018 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
0019 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
0020 static struct clk_hw *clkout_clk[2];
0021
0022 #define PRCC_SHOW(clk, base, bit) \
0023     clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
0024 #define PRCC_PCLK_STORE(clk, base, bit) \
0025     prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
0026 #define PRCC_KCLK_STORE(clk, base, bit)        \
0027     prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
0028
0029 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
0030                      void *data)
0031 {
0032     struct clk **clk_data = data;
0033     unsigned int base, bit;
0034
0035     if (clkspec->args_count != 2)
0036         return  ERR_PTR(-EINVAL);
0037
0038     base = clkspec->args[0];
0039     bit = clkspec->args[1];
0040
0041     if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
0042         pr_err("%s: invalid PRCC base %d\n", __func__, base);
0043         return ERR_PTR(-EINVAL);
0044     }
0045
0046     return PRCC_SHOW(clk_data, base, bit);
0047 }
0048
0049 static struct clk_hw_onecell_data u8500_prcmu_hw_clks = {
0050     .hws = {
0051         /*
0052          * This assignment makes sure the dynamic array
0053          * gets the right size.
0054          */
0055         [PRCMU_NUM_CLKS] = NULL,
0056     },
0057     .num = PRCMU_NUM_CLKS,
0058 };
0059
0060 /* Essentially names for the first PRCMU_CLKSRC_* defines */
0061 static const char * const u8500_clkout_parents[] = {
0062     "clk38m_to_clkgen",
0063     "aclk",
0064     /* Just called "sysclk" in documentation */
0065     "ab8500_sysclk",
0066     "lcdclk",
0067     "sdmmcclk",
0068     "tvclk",
0069     "timclk",
0070     /* CLK009 is not implemented, add it if you need it */
0071     "clk009",
0072 };
0073
0074 static struct clk_hw *ux500_clkout_get(struct of_phandle_args *clkspec,
0075                        void *data)
0076 {
0077     u32 id, source, divider;
0078     struct clk_hw *clkout;
0079
0080     if (clkspec->args_count != 3)
0081         return  ERR_PTR(-EINVAL);
0082
0083     id = clkspec->args[0];
0084     source = clkspec->args[1];
0085     divider = clkspec->args[2];
0086
0087     if (id > 1) {
0088         pr_err("%s: invalid clkout ID %d\n", __func__, id);
0089         return ERR_PTR(-EINVAL);
0090     }
0091
0092     if (clkout_clk[id]) {
0093         pr_info("%s: clkout%d already registered, not reconfiguring\n",
0094             __func__, id + 1);
0095         return clkout_clk[id];
0096     }
0097
0098     if (source > 7) {
0099         pr_err("%s: invalid source ID %d\n", __func__, source);
0100         return ERR_PTR(-EINVAL);
0101     }
0102
0103     if (divider == 0 || divider > 63) {
0104         pr_err("%s: invalid divider %d\n", __func__, divider);
0105         return ERR_PTR(-EINVAL);
0106     }
0107
0108     pr_debug("registering clkout%d with source %d and divider %d\n",
0109          id + 1, source, divider);
0110
0111     clkout = clk_reg_prcmu_clkout(id ? "clkout2" : "clkout1",
0112                       u8500_clkout_parents,
0113                       ARRAY_SIZE(u8500_clkout_parents),
0114                       source, divider);
0115     if (IS_ERR(clkout)) {
0116         pr_err("failed to register clkout%d\n",  id + 1);
0117         return ERR_CAST(clkout);
0118     }
0119
0120     clkout_clk[id] = clkout;
0121
0122     return clkout;
0123 }
0124
0125 static void u8500_clk_init(struct device_node *np)
0126 {
0127     struct prcmu_fw_version *fw_version;
0128     struct device_node *child = NULL;
0129     const char *sgaclk_parent = NULL;
0130     struct clk *clk, *rtc_clk, *twd_clk;
0131     u32 bases[CLKRST_MAX];
0132     struct u8500_prcc_reset *rstc;
0133     int i;
0134
0135     /*
0136      * We allocate the reset controller here so that we can fill in the
0137      * base addresses properly and pass to the reset controller init
0138      * function later on.
0139      */
0140     rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
0141     if (!rstc)
0142         return;
0143
0144     for (i = 0; i < ARRAY_SIZE(bases); i++) {
0145         struct resource r;
0146
0147         if (of_address_to_resource(np, i, &r))
0148             /* Not much choice but to continue */
0149             pr_err("failed to get CLKRST %d base address\n",
0150                    i + 1);
0151         bases[i] = r.start;
0152         rstc->phy_base[i] = r.start;
0153     }
0154
0155     /* Clock sources */
0156     u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC0] =
0157         clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
0158                    CLK_IGNORE_UNUSED);
0159
0160     u8500_prcmu_hw_clks.hws[PRCMU_PLLSOC1] =
0161         clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
0162                    CLK_IGNORE_UNUSED);
0163
0164     u8500_prcmu_hw_clks.hws[PRCMU_PLLDDR] =
0165         clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
0166                    CLK_IGNORE_UNUSED);
0167
0168     /*
0169      * Read-only clocks that only return their current rate, only used
0170      * as parents to other clocks and not visible in the device tree.
0171      * clk38m_to_clkgen is the same as the SYSCLK, i.e. the root clock.
0172      */
0173     clk_reg_prcmu_rate("clk38m_to_clkgen", NULL, PRCMU_SYSCLK,
0174                CLK_IGNORE_UNUSED);
0175     clk_reg_prcmu_rate("aclk", NULL, PRCMU_ACLK,
0176                CLK_IGNORE_UNUSED);
0177
0178     /* TODO: add CLK009 if needed */
0179
0180     rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
0181                 CLK_IGNORE_UNUSED,
0182                 32768);
0183
0184     /* PRCMU clocks */
0185     fw_version = prcmu_get_fw_version();
0186     if (fw_version != NULL) {
0187         switch (fw_version->project) {
0188         case PRCMU_FW_PROJECT_U8500_C2:
0189         case PRCMU_FW_PROJECT_U8500_SSG1:
0190         case PRCMU_FW_PROJECT_U8520:
0191         case PRCMU_FW_PROJECT_U8420:
0192         case PRCMU_FW_PROJECT_U8420_SYSCLK:
0193         case PRCMU_FW_PROJECT_U8500_SSG2:
0194             sgaclk_parent = "soc0_pll";
0195             break;
0196         default:
0197             break;
0198         }
0199     }
0200
0201     if (sgaclk_parent)
0202         u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] =
0203             clk_reg_prcmu_gate("sgclk", sgaclk_parent,
0204                        PRCMU_SGACLK, 0);
0205     else
0206         u8500_prcmu_hw_clks.hws[PRCMU_SGACLK] =
0207             clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
0208
0209     u8500_prcmu_hw_clks.hws[PRCMU_UARTCLK] =
0210         clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
0211     u8500_prcmu_hw_clks.hws[PRCMU_MSP02CLK] =
0212         clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
0213     u8500_prcmu_hw_clks.hws[PRCMU_MSP1CLK] =
0214         clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
0215     u8500_prcmu_hw_clks.hws[PRCMU_I2CCLK] =
0216         clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
0217     u8500_prcmu_hw_clks.hws[PRCMU_SLIMCLK] =
0218         clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
0219     u8500_prcmu_hw_clks.hws[PRCMU_PER1CLK] =
0220         clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
0221     u8500_prcmu_hw_clks.hws[PRCMU_PER2CLK] =
0222         clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
0223     u8500_prcmu_hw_clks.hws[PRCMU_PER3CLK] =
0224         clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
0225     u8500_prcmu_hw_clks.hws[PRCMU_PER5CLK] =
0226         clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
0227     u8500_prcmu_hw_clks.hws[PRCMU_PER6CLK] =
0228         clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
0229     u8500_prcmu_hw_clks.hws[PRCMU_PER7CLK] =
0230         clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
0231     u8500_prcmu_hw_clks.hws[PRCMU_LCDCLK] =
0232         clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
0233                        CLK_SET_RATE_GATE);
0234     u8500_prcmu_hw_clks.hws[PRCMU_BMLCLK] =
0235         clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
0236     u8500_prcmu_hw_clks.hws[PRCMU_HSITXCLK] =
0237         clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
0238                        CLK_SET_RATE_GATE);
0239     u8500_prcmu_hw_clks.hws[PRCMU_HSIRXCLK] =
0240         clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
0241                        CLK_SET_RATE_GATE);
0242     u8500_prcmu_hw_clks.hws[PRCMU_HDMICLK] =
0243         clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
0244                        CLK_SET_RATE_GATE);
0245     u8500_prcmu_hw_clks.hws[PRCMU_APEATCLK] =
0246         clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
0247     u8500_prcmu_hw_clks.hws[PRCMU_APETRACECLK] =
0248         clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
0249                        CLK_SET_RATE_GATE);
0250     u8500_prcmu_hw_clks.hws[PRCMU_MCDECLK] =
0251         clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
0252     u8500_prcmu_hw_clks.hws[PRCMU_IPI2CCLK] =
0253         clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
0254     u8500_prcmu_hw_clks.hws[PRCMU_DSIALTCLK] =
0255         clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
0256     u8500_prcmu_hw_clks.hws[PRCMU_DMACLK] =
0257         clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
0258     u8500_prcmu_hw_clks.hws[PRCMU_B2R2CLK] =
0259         clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
0260     u8500_prcmu_hw_clks.hws[PRCMU_TVCLK] =
0261         clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
0262                        CLK_SET_RATE_GATE);
0263     u8500_prcmu_hw_clks.hws[PRCMU_SSPCLK] =
0264         clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
0265     u8500_prcmu_hw_clks.hws[PRCMU_RNGCLK] =
0266         clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
0267     u8500_prcmu_hw_clks.hws[PRCMU_UICCCLK] =
0268         clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
0269     u8500_prcmu_hw_clks.hws[PRCMU_TIMCLK] =
0270         clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
0271     u8500_prcmu_hw_clks.hws[PRCMU_SYSCLK] =
0272         clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
0273     u8500_prcmu_hw_clks.hws[PRCMU_SDMMCCLK] =
0274         clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL,
0275                         PRCMU_SDMMCCLK, 100000000,
0276                         CLK_SET_RATE_GATE);
0277     u8500_prcmu_hw_clks.hws[PRCMU_PLLDSI] =
0278         clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
0279                        PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
0280     u8500_prcmu_hw_clks.hws[PRCMU_DSI0CLK] =
0281         clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
0282                        PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
0283     u8500_prcmu_hw_clks.hws[PRCMU_DSI1CLK] =
0284         clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
0285                        PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
0286     u8500_prcmu_hw_clks.hws[PRCMU_DSI0ESCCLK] =
0287         clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
0288                        PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
0289     u8500_prcmu_hw_clks.hws[PRCMU_DSI1ESCCLK] =
0290         clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
0291                        PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
0292     u8500_prcmu_hw_clks.hws[PRCMU_DSI2ESCCLK] =
0293         clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
0294                        PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
0295     u8500_prcmu_hw_clks.hws[PRCMU_ARMSS] =
0296         clk_reg_prcmu_scalable_rate("armss", NULL,
0297                         PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
0298
0299     twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
0300                 CLK_IGNORE_UNUSED, 1, 2);
0301
0302     /* PRCC P-clocks */
0303     clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
0304                 BIT(0), 0);
0305     PRCC_PCLK_STORE(clk, 1, 0);
0306
0307     clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
0308                 BIT(1), 0);
0309     PRCC_PCLK_STORE(clk, 1, 1);
0310
0311     clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
0312                 BIT(2), 0);
0313     PRCC_PCLK_STORE(clk, 1, 2);
0314
0315     clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
0316                 BIT(3), 0);
0317     PRCC_PCLK_STORE(clk, 1, 3);
0318
0319     clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
0320                 BIT(4), 0);
0321     PRCC_PCLK_STORE(clk, 1, 4);
0322
0323     clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
0324                 BIT(5), 0);
0325     PRCC_PCLK_STORE(clk, 1, 5);
0326
0327     clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
0328                 BIT(6), 0);
0329     PRCC_PCLK_STORE(clk, 1, 6);
0330
0331     clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
0332                 BIT(7), 0);
0333     PRCC_PCLK_STORE(clk, 1, 7);
0334
0335     clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
0336                 BIT(8), 0);
0337     PRCC_PCLK_STORE(clk, 1, 8);
0338
0339     clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
0340                 BIT(9), 0);
0341     PRCC_PCLK_STORE(clk, 1, 9);
0342
0343     clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
0344                 BIT(10), 0);
0345     PRCC_PCLK_STORE(clk, 1, 10);
0346
0347     clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
0348                 BIT(11), 0);
0349     PRCC_PCLK_STORE(clk, 1, 11);
0350
0351     clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
0352                 BIT(0), 0);
0353     PRCC_PCLK_STORE(clk, 2, 0);
0354
0355     clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
0356                 BIT(1), 0);
0357     PRCC_PCLK_STORE(clk, 2, 1);
0358
0359     clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
0360                 BIT(2), 0);
0361     PRCC_PCLK_STORE(clk, 2, 2);
0362
0363     clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
0364                 BIT(3), 0);
0365     PRCC_PCLK_STORE(clk, 2, 3);
0366
0367     clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
0368                 BIT(4), 0);
0369     PRCC_PCLK_STORE(clk, 2, 4);
0370
0371     clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
0372                 BIT(5), 0);
0373     PRCC_PCLK_STORE(clk, 2, 5);
0374
0375     clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
0376                 BIT(6), 0);
0377     PRCC_PCLK_STORE(clk, 2, 6);
0378
0379     clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
0380                 BIT(7), 0);
0381     PRCC_PCLK_STORE(clk, 2, 7);
0382
0383     clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
0384                 BIT(8), 0);
0385     PRCC_PCLK_STORE(clk, 2, 8);
0386
0387     clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
0388                 BIT(9), 0);
0389     PRCC_PCLK_STORE(clk, 2, 9);
0390
0391     clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
0392                 BIT(10), 0);
0393     PRCC_PCLK_STORE(clk, 2, 10);
0394
0395     clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
0396                 BIT(11), 0);
0397     PRCC_PCLK_STORE(clk, 2, 11);
0398
0399     clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
0400                 BIT(12), 0);
0401     PRCC_PCLK_STORE(clk, 2, 12);
0402
0403     clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
0404                 BIT(0), 0);
0405     PRCC_PCLK_STORE(clk, 3, 0);
0406
0407     clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
0408                 BIT(1), 0);
0409     PRCC_PCLK_STORE(clk, 3, 1);
0410
0411     clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
0412                 BIT(2), 0);
0413     PRCC_PCLK_STORE(clk, 3, 2);
0414
0415     clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
0416                 BIT(3), 0);
0417     PRCC_PCLK_STORE(clk, 3, 3);
0418
0419     clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
0420                 BIT(4), 0);
0421     PRCC_PCLK_STORE(clk, 3, 4);
0422
0423     clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
0424                 BIT(5), 0);
0425     PRCC_PCLK_STORE(clk, 3, 5);
0426
0427     clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
0428                 BIT(6), 0);
0429     PRCC_PCLK_STORE(clk, 3, 6);
0430
0431     clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
0432                 BIT(7), 0);
0433     PRCC_PCLK_STORE(clk, 3, 7);
0434
0435     clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
0436                 BIT(8), 0);
0437     PRCC_PCLK_STORE(clk, 3, 8);
0438
0439     clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
0440                 BIT(0), 0);
0441     PRCC_PCLK_STORE(clk, 5, 0);
0442
0443     clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
0444                 BIT(1), 0);
0445     PRCC_PCLK_STORE(clk, 5, 1);
0446
0447     clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
0448                 BIT(0), 0);
0449     PRCC_PCLK_STORE(clk, 6, 0);
0450
0451     clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
0452                 BIT(1), 0);
0453     PRCC_PCLK_STORE(clk, 6, 1);
0454
0455     clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
0456                 BIT(2), 0);
0457     PRCC_PCLK_STORE(clk, 6, 2);
0458
0459     clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
0460                 BIT(3), 0);
0461     PRCC_PCLK_STORE(clk, 6, 3);
0462
0463     clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
0464                 BIT(4), 0);
0465     PRCC_PCLK_STORE(clk, 6, 4);
0466
0467     clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
0468                 BIT(5), 0);
0469     PRCC_PCLK_STORE(clk, 6, 5);
0470
0471     clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
0472                 BIT(6), 0);
0473     PRCC_PCLK_STORE(clk, 6, 6);
0474
0475     clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
0476                 BIT(7), 0);
0477     PRCC_PCLK_STORE(clk, 6, 7);
0478
0479     /* PRCC K-clocks
0480      *
0481      * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
0482      * by enabling just the K-clock, even if it is not a valid parent to
0483      * the K-clock. Until drivers get fixed we might need some kind of
0484      * "parent muxed join".
0485      */
0486
0487     /* Periph1 */
0488     clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
0489             bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
0490     PRCC_KCLK_STORE(clk, 1, 0);
0491
0492     clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
0493             bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
0494     PRCC_KCLK_STORE(clk, 1, 1);
0495
0496     clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
0497             bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
0498     PRCC_KCLK_STORE(clk, 1, 2);
0499
0500     clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
0501             bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
0502     PRCC_KCLK_STORE(clk, 1, 3);
0503
0504     clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
0505             bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
0506     PRCC_KCLK_STORE(clk, 1, 4);
0507
0508     clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
0509             bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
0510     PRCC_KCLK_STORE(clk, 1, 5);
0511
0512     clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
0513             bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
0514     PRCC_KCLK_STORE(clk, 1, 6);
0515
0516     clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
0517             bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
0518     PRCC_KCLK_STORE(clk, 1, 8);
0519
0520     clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
0521             bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
0522     PRCC_KCLK_STORE(clk, 1, 9);
0523
0524     clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
0525             bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
0526     PRCC_KCLK_STORE(clk, 1, 10);
0527
0528     /* Periph2 */
0529     clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
0530             bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
0531     PRCC_KCLK_STORE(clk, 2, 0);
0532
0533     clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
0534             bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
0535     PRCC_KCLK_STORE(clk, 2, 2);
0536
0537     clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
0538             bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
0539     PRCC_KCLK_STORE(clk, 2, 3);
0540
0541     clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
0542             bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
0543     PRCC_KCLK_STORE(clk, 2, 4);
0544
0545     clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
0546             bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
0547     PRCC_KCLK_STORE(clk, 2, 5);
0548
0549     /* Note that rate is received from parent. */
0550     clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
0551             bases[CLKRST2_INDEX], BIT(6),
0552             CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
0553     PRCC_KCLK_STORE(clk, 2, 6);
0554
0555     clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
0556             bases[CLKRST2_INDEX], BIT(7),
0557             CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
0558     PRCC_KCLK_STORE(clk, 2, 7);
0559
0560     /* Periph3 */
0561     clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
0562             bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
0563     PRCC_KCLK_STORE(clk, 3, 1);
0564
0565     clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
0566             bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
0567     PRCC_KCLK_STORE(clk, 3, 2);
0568
0569     clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
0570             bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
0571     PRCC_KCLK_STORE(clk, 3, 3);
0572
0573     clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
0574             bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
0575     PRCC_KCLK_STORE(clk, 3, 4);
0576
0577     clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
0578             bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
0579     PRCC_KCLK_STORE(clk, 3, 5);
0580
0581     clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
0582             bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
0583     PRCC_KCLK_STORE(clk, 3, 6);
0584
0585     clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
0586             bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
0587     PRCC_KCLK_STORE(clk, 3, 7);
0588
0589     /* Periph6 */
0590     clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
0591             bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
0592     PRCC_KCLK_STORE(clk, 6, 0);
0593
0594     for_each_child_of_node(np, child) {
0595         if (of_node_name_eq(child, "prcmu-clock"))
0596             of_clk_add_hw_provider(child, of_clk_hw_onecell_get,
0597                            &u8500_prcmu_hw_clks);
0598
0599         if (of_node_name_eq(child, "clkout-clock"))
0600             of_clk_add_hw_provider(child, ux500_clkout_get, NULL);
0601
0602         if (of_node_name_eq(child, "prcc-periph-clock"))
0603             of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
0604
0605         if (of_node_name_eq(child, "prcc-kernel-clock"))
0606             of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
0607
0608         if (of_node_name_eq(child, "rtc32k-clock"))
0609             of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
0610
0611         if (of_node_name_eq(child, "smp-twd-clock"))
0612             of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
0613
0614         if (of_node_name_eq(child, "prcc-reset-controller"))
0615             u8500_prcc_reset_init(child, rstc);
0616     }
0617 }
0618 CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);