clk/ux500/reset-prcc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Reset controller portions for the U8500 PRCC
0004  * Copyright (C) 2021 Linus Walleij <linus.walleij@linaro.org>
0005  */
0006 #include <linux/of.h>
0007 #include <linux/of_address.h>
0008 #include <linux/slab.h>
0009 #include <linux/io.h>
0010 #include <linux/err.h>
0011 #include <linux/types.h>
0012 #include <linux/reset-controller.h>
0013 #include <linux/bits.h>
0014 #include <linux/delay.h>
0015
0016 #include "prcc.h"
0017 #include "reset-prcc.h"
0018
0019 #define to_u8500_prcc_reset(p) container_of((p), struct u8500_prcc_reset, rcdev)
0020
0021 /* This macro flattens the 2-dimensional PRCC numberspace */
0022 #define PRCC_RESET_LINE(prcc_num, bit) \
0023     (((prcc_num) * PRCC_PERIPHS_PER_CLUSTER) + (bit))
0024
0025 /*
0026  * Reset registers in each PRCC - the reset lines are active low
0027  * so what you need to do is write a bit for the peripheral you
0028  * want to put into reset into the CLEAR register, this will assert
0029  * the reset by pulling the line low. SET take the device out of
0030  * reset. The status reflects the actual state of the line.
0031  */
0032 #define PRCC_K_SOFTRST_SET      0x018
0033 #define PRCC_K_SOFTRST_CLEAR        0x01c
0034 #define PRCC_K_RST_STATUS       0x020
0035
0036 static int prcc_num_to_index(unsigned int num)
0037 {
0038     switch (num) {
0039     case 1:
0040         return CLKRST1_INDEX;
0041     case 2:
0042         return CLKRST2_INDEX;
0043     case 3:
0044         return CLKRST3_INDEX;
0045     case 5:
0046         return CLKRST5_INDEX;
0047     case 6:
0048         return CLKRST6_INDEX;
0049     }
0050     return -EINVAL;
0051 }
0052
0053 static void __iomem *u8500_prcc_reset_base(struct u8500_prcc_reset *ur,
0054                        unsigned long id)
0055 {
0056     unsigned int prcc_num, index;
0057
0058     prcc_num = id / PRCC_PERIPHS_PER_CLUSTER;
0059     index = prcc_num_to_index(prcc_num);
0060
0061     if (index >= ARRAY_SIZE(ur->base))
0062         return NULL;
0063
0064     return ur->base[index];
0065 }
0066
0067 static int u8500_prcc_reset(struct reset_controller_dev *rcdev,
0068                 unsigned long id)
0069 {
0070     struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev);
0071     void __iomem *base = u8500_prcc_reset_base(ur, id);
0072     unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER;
0073
0074     pr_debug("PRCC cycle reset id %lu, bit %u\n", id, bit);
0075
0076     /*
0077      * Assert reset and then release it. The one microsecond
0078      * delay is found in the vendor reference code.
0079      */
0080     writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR);
0081     udelay(1);
0082     writel(BIT(bit), base + PRCC_K_SOFTRST_SET);
0083     udelay(1);
0084
0085     return 0;
0086 }
0087
0088 static int u8500_prcc_reset_assert(struct reset_controller_dev *rcdev,
0089                    unsigned long id)
0090 {
0091     struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev);
0092     void __iomem *base = u8500_prcc_reset_base(ur, id);
0093     unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER;
0094
0095     pr_debug("PRCC assert reset id %lu, bit %u\n", id, bit);
0096     writel(BIT(bit), base + PRCC_K_SOFTRST_CLEAR);
0097
0098     return 0;
0099 }
0100
0101 static int u8500_prcc_reset_deassert(struct reset_controller_dev *rcdev,
0102                      unsigned long id)
0103 {
0104     struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev);
0105     void __iomem *base = u8500_prcc_reset_base(ur, id);
0106     unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER;
0107
0108     pr_debug("PRCC deassert reset id %lu, bit %u\n", id, bit);
0109     writel(BIT(bit), base + PRCC_K_SOFTRST_SET);
0110
0111     return 0;
0112 }
0113
0114 static int u8500_prcc_reset_status(struct reset_controller_dev *rcdev,
0115                    unsigned long id)
0116 {
0117     struct u8500_prcc_reset *ur = to_u8500_prcc_reset(rcdev);
0118     void __iomem *base = u8500_prcc_reset_base(ur, id);
0119     unsigned int bit = id % PRCC_PERIPHS_PER_CLUSTER;
0120     u32 val;
0121
0122     pr_debug("PRCC check status on reset line id %lu, bit %u\n", id, bit);
0123     val = readl(base + PRCC_K_RST_STATUS);
0124
0125     /* Active low so return the inverse value of the bit */
0126     return !(val & BIT(bit));
0127 }
0128
0129 static const struct reset_control_ops u8500_prcc_reset_ops = {
0130     .reset = u8500_prcc_reset,
0131     .assert = u8500_prcc_reset_assert,
0132     .deassert = u8500_prcc_reset_deassert,
0133     .status = u8500_prcc_reset_status,
0134 };
0135
0136 static int u8500_prcc_reset_xlate(struct reset_controller_dev *rcdev,
0137                   const struct of_phandle_args *reset_spec)
0138 {
0139     unsigned int prcc_num, bit;
0140
0141     if (reset_spec->args_count != 2)
0142         return -EINVAL;
0143
0144     prcc_num = reset_spec->args[0];
0145     bit = reset_spec->args[1];
0146
0147     if (prcc_num != 1 && prcc_num != 2 && prcc_num != 3 &&
0148         prcc_num != 5 && prcc_num != 6) {
0149         pr_err("%s: invalid PRCC %d\n", __func__, prcc_num);
0150         return -EINVAL;
0151     }
0152
0153     pr_debug("located reset line %d at PRCC %d bit %d\n",
0154          PRCC_RESET_LINE(prcc_num, bit), prcc_num, bit);
0155
0156     return PRCC_RESET_LINE(prcc_num, bit);
0157 }
0158
0159 void u8500_prcc_reset_init(struct device_node *np, struct u8500_prcc_reset *ur)
0160 {
0161     struct reset_controller_dev *rcdev = &ur->rcdev;
0162     int ret;
0163     int i;
0164
0165     for (i = 0; i < CLKRST_MAX; i++) {
0166         ur->base[i] = ioremap(ur->phy_base[i], SZ_4K);
0167         if (!ur->base[i])
0168             pr_err("PRCC failed to remap for reset base %d (%08x)\n",
0169                    i, ur->phy_base[i]);
0170     }
0171
0172     rcdev->owner = THIS_MODULE;
0173     rcdev->ops = &u8500_prcc_reset_ops;
0174     rcdev->of_node = np;
0175     rcdev->of_reset_n_cells = 2;
0176     rcdev->of_xlate = u8500_prcc_reset_xlate;
0177
0178     ret = reset_controller_register(rcdev);
0179     if (ret)
0180         pr_err("PRCC failed to register reset controller\n");
0181 }