clk/ux500/clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Clocks for ux500 platforms
0004  *
0005  * Copyright (C) 2012 ST-Ericsson SA
0006  * Author: Ulf Hansson <ulf.hansson@linaro.org>
0007  */
0008
0009 #ifndef __UX500_CLK_H
0010 #define __UX500_CLK_H
0011
0012 #include <linux/device.h>
0013 #include <linux/types.h>
0014
0015 struct clk;
0016 struct clk_hw;
0017
0018 struct clk *clk_reg_prcc_pclk(const char *name,
0019                   const char *parent_name,
0020                   resource_size_t phy_base,
0021                   u32 cg_sel,
0022                   unsigned long flags);
0023
0024 struct clk *clk_reg_prcc_kclk(const char *name,
0025                   const char *parent_name,
0026                   resource_size_t phy_base,
0027                   u32 cg_sel,
0028                   unsigned long flags);
0029
0030 struct clk_hw *clk_reg_prcmu_scalable(const char *name,
0031                       const char *parent_name,
0032                       u8 cg_sel,
0033                       unsigned long rate,
0034                       unsigned long flags);
0035
0036 struct clk_hw *clk_reg_prcmu_gate(const char *name,
0037                   const char *parent_name,
0038                   u8 cg_sel,
0039                   unsigned long flags);
0040
0041 struct clk_hw *clk_reg_prcmu_scalable_rate(const char *name,
0042                        const char *parent_name,
0043                        u8 cg_sel,
0044                        unsigned long rate,
0045                        unsigned long flags);
0046
0047 struct clk_hw *clk_reg_prcmu_rate(const char *name,
0048                   const char *parent_name,
0049                   u8 cg_sel,
0050                   unsigned long flags);
0051
0052 struct clk_hw *clk_reg_prcmu_opp_gate(const char *name,
0053                       const char *parent_name,
0054                       u8 cg_sel,
0055                       unsigned long flags);
0056
0057 struct clk_hw *clk_reg_prcmu_opp_volt_scalable(const char *name,
0058                            const char *parent_name,
0059                            u8 cg_sel,
0060                            unsigned long rate,
0061                            unsigned long flags);
0062
0063 struct clk_hw *clk_reg_prcmu_clkout(const char *name,
0064                     const char * const *parent_names,
0065                     int num_parents,
0066                     u8 source, u8 divider);
0067
0068 struct clk *clk_reg_sysctrl_gate(struct device *dev,
0069                  const char *name,
0070                  const char *parent_name,
0071                  u16 reg_sel,
0072                  u8 reg_mask,
0073                  u8 reg_bits,
0074                  unsigned long enable_delay_us,
0075                  unsigned long flags);
0076
0077 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
0078                         const char *name,
0079                         const char *parent_name,
0080                         u16 reg_sel,
0081                         u8 reg_mask,
0082                         u8 reg_bits,
0083                         unsigned long rate,
0084                         unsigned long enable_delay_us,
0085                         unsigned long flags);
0086
0087 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
0088                        const char *name,
0089                        const char **parent_names,
0090                        u8 num_parents,
0091                        u16 *reg_sel,
0092                        u8 *reg_mask,
0093                        u8 *reg_bits,
0094                        unsigned long flags);
0095
0096 #endif /* __UX500_CLK_H */