clk/ux500/clk-sysctrl.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Sysctrl clock implementation for ux500 platform.
0004  *
0005  * Copyright (C) 2013 ST-Ericsson SA
0006  * Author: Ulf Hansson <ulf.hansson@linaro.org>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/mfd/abx500/ab8500-sysctrl.h>
0011 #include <linux/device.h>
0012 #include <linux/slab.h>
0013 #include <linux/delay.h>
0014 #include <linux/io.h>
0015 #include <linux/err.h>
0016 #include "clk.h"
0017
0018 #define SYSCTRL_MAX_NUM_PARENTS 4
0019
0020 #define to_clk_sysctrl(_hw) container_of(_hw, struct clk_sysctrl, hw)
0021
0022 struct clk_sysctrl {
0023     struct clk_hw hw;
0024     struct device *dev;
0025     u8 parent_index;
0026     u16 reg_sel[SYSCTRL_MAX_NUM_PARENTS];
0027     u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS];
0028     u8 reg_bits[SYSCTRL_MAX_NUM_PARENTS];
0029     unsigned long rate;
0030     unsigned long enable_delay_us;
0031 };
0032
0033 /* Sysctrl clock operations. */
0034
0035 static int clk_sysctrl_prepare(struct clk_hw *hw)
0036 {
0037     int ret;
0038     struct clk_sysctrl *clk = to_clk_sysctrl(hw);
0039
0040     ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0],
0041                 clk->reg_bits[0]);
0042
0043     if (!ret && clk->enable_delay_us)
0044         usleep_range(clk->enable_delay_us, clk->enable_delay_us +
0045                  (clk->enable_delay_us >> 2));
0046
0047     return ret;
0048 }
0049
0050 static void clk_sysctrl_unprepare(struct clk_hw *hw)
0051 {
0052     struct clk_sysctrl *clk = to_clk_sysctrl(hw);
0053     if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0]))
0054         dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n",
0055             __func__, clk_hw_get_name(hw));
0056 }
0057
0058 static unsigned long clk_sysctrl_recalc_rate(struct clk_hw *hw,
0059                     unsigned long parent_rate)
0060 {
0061     struct clk_sysctrl *clk = to_clk_sysctrl(hw);
0062     return clk->rate;
0063 }
0064
0065 static int clk_sysctrl_set_parent(struct clk_hw *hw, u8 index)
0066 {
0067     struct clk_sysctrl *clk = to_clk_sysctrl(hw);
0068     u8 old_index = clk->parent_index;
0069     int ret = 0;
0070
0071     if (clk->reg_sel[old_index]) {
0072         ret = ab8500_sysctrl_clear(clk->reg_sel[old_index],
0073                     clk->reg_mask[old_index]);
0074         if (ret)
0075             return ret;
0076     }
0077
0078     if (clk->reg_sel[index]) {
0079         ret = ab8500_sysctrl_write(clk->reg_sel[index],
0080                     clk->reg_mask[index],
0081                     clk->reg_bits[index]);
0082         if (ret) {
0083             if (clk->reg_sel[old_index])
0084                 ab8500_sysctrl_write(clk->reg_sel[old_index],
0085                         clk->reg_mask[old_index],
0086                         clk->reg_bits[old_index]);
0087             return ret;
0088         }
0089     }
0090     clk->parent_index = index;
0091
0092     return ret;
0093 }
0094
0095 static u8 clk_sysctrl_get_parent(struct clk_hw *hw)
0096 {
0097     struct clk_sysctrl *clk = to_clk_sysctrl(hw);
0098     return clk->parent_index;
0099 }
0100
0101 static const struct clk_ops clk_sysctrl_gate_ops = {
0102     .prepare = clk_sysctrl_prepare,
0103     .unprepare = clk_sysctrl_unprepare,
0104 };
0105
0106 static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = {
0107     .prepare = clk_sysctrl_prepare,
0108     .unprepare = clk_sysctrl_unprepare,
0109     .recalc_rate = clk_sysctrl_recalc_rate,
0110 };
0111
0112 static const struct clk_ops clk_sysctrl_set_parent_ops = {
0113     .set_parent = clk_sysctrl_set_parent,
0114     .get_parent = clk_sysctrl_get_parent,
0115 };
0116
0117 static struct clk *clk_reg_sysctrl(struct device *dev,
0118                 const char *name,
0119                 const char **parent_names,
0120                 u8 num_parents,
0121                 u16 *reg_sel,
0122                 u8 *reg_mask,
0123                 u8 *reg_bits,
0124                 unsigned long rate,
0125                 unsigned long enable_delay_us,
0126                 unsigned long flags,
0127                 const struct clk_ops *clk_sysctrl_ops)
0128 {
0129     struct clk_sysctrl *clk;
0130     struct clk_init_data clk_sysctrl_init;
0131     struct clk *clk_reg;
0132     int i;
0133
0134     if (!dev)
0135         return ERR_PTR(-EINVAL);
0136
0137     if (!name || (num_parents > SYSCTRL_MAX_NUM_PARENTS)) {
0138         dev_err(dev, "clk_sysctrl: invalid arguments passed\n");
0139         return ERR_PTR(-EINVAL);
0140     }
0141
0142     clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
0143     if (!clk)
0144         return ERR_PTR(-ENOMEM);
0145
0146     /* set main clock registers */
0147     clk->reg_sel[0] = reg_sel[0];
0148     clk->reg_bits[0] = reg_bits[0];
0149     clk->reg_mask[0] = reg_mask[0];
0150
0151     /* handle clocks with more than one parent */
0152     for (i = 1; i < num_parents; i++) {
0153         clk->reg_sel[i] = reg_sel[i];
0154         clk->reg_bits[i] = reg_bits[i];
0155         clk->reg_mask[i] = reg_mask[i];
0156     }
0157
0158     clk->parent_index = 0;
0159     clk->rate = rate;
0160     clk->enable_delay_us = enable_delay_us;
0161     clk->dev = dev;
0162
0163     clk_sysctrl_init.name = name;
0164     clk_sysctrl_init.ops = clk_sysctrl_ops;
0165     clk_sysctrl_init.flags = flags;
0166     clk_sysctrl_init.parent_names = parent_names;
0167     clk_sysctrl_init.num_parents = num_parents;
0168     clk->hw.init = &clk_sysctrl_init;
0169
0170     clk_reg = devm_clk_register(clk->dev, &clk->hw);
0171     if (IS_ERR(clk_reg))
0172         dev_err(dev, "clk_sysctrl: clk_register failed\n");
0173
0174     return clk_reg;
0175 }
0176
0177 struct clk *clk_reg_sysctrl_gate(struct device *dev,
0178                 const char *name,
0179                 const char *parent_name,
0180                 u16 reg_sel,
0181                 u8 reg_mask,
0182                 u8 reg_bits,
0183                 unsigned long enable_delay_us,
0184                 unsigned long flags)
0185 {
0186     const char **parent_names = (parent_name ? &parent_name : NULL);
0187     u8 num_parents = (parent_name ? 1 : 0);
0188
0189     return clk_reg_sysctrl(dev, name, parent_names, num_parents,
0190             &reg_sel, &reg_mask, &reg_bits, 0, enable_delay_us,
0191             flags, &clk_sysctrl_gate_ops);
0192 }
0193
0194 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
0195                     const char *name,
0196                     const char *parent_name,
0197                     u16 reg_sel,
0198                     u8 reg_mask,
0199                     u8 reg_bits,
0200                     unsigned long rate,
0201                     unsigned long enable_delay_us,
0202                     unsigned long flags)
0203 {
0204     const char **parent_names = (parent_name ? &parent_name : NULL);
0205     u8 num_parents = (parent_name ? 1 : 0);
0206
0207     return clk_reg_sysctrl(dev, name, parent_names, num_parents,
0208             &reg_sel, &reg_mask, &reg_bits,
0209             rate, enable_delay_us, flags,
0210             &clk_sysctrl_gate_fixed_rate_ops);
0211 }
0212
0213 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
0214                 const char *name,
0215                 const char **parent_names,
0216                 u8 num_parents,
0217                 u16 *reg_sel,
0218                 u8 *reg_mask,
0219                 u8 *reg_bits,
0220                 unsigned long flags)
0221 {
0222     return clk_reg_sysctrl(dev, name, parent_names, num_parents,
0223             reg_sel, reg_mask, reg_bits, 0, 0, flags,
0224             &clk_sysctrl_set_parent_ops);
0225 }