clk/ux500/abx500-clk.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * abx500 clock implementation for ux500 platform.
0004  *
0005  * Copyright (C) 2012 ST-Ericsson SA
0006  * Author: Ulf Hansson <ulf.hansson@linaro.org>
0007  */
0008
0009 #include <linux/err.h>
0010 #include <linux/module.h>
0011 #include <linux/device.h>
0012 #include <linux/of.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/mfd/abx500/ab8500.h>
0015 #include <linux/mfd/abx500/ab8500-sysctrl.h>
0016 #include <linux/clkdev.h>
0017 #include <linux/clk-provider.h>
0018 #include <dt-bindings/clock/ste-ab8500.h>
0019 #include "clk.h"
0020
0021 #define AB8500_NUM_CLKS 6
0022
0023 static struct clk *ab8500_clks[AB8500_NUM_CLKS];
0024 static struct clk_onecell_data ab8500_clk_data;
0025
0026 /* Clock definitions for ab8500 */
0027 static int ab8500_reg_clks(struct device *dev)
0028 {
0029     int ret;
0030     struct clk *clk;
0031     struct device_node *np = dev->of_node;
0032     const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
0033     u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
0034     u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
0035     u8 intclk_reg_bits[] = {
0036         0 ,
0037         (1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
0038     };
0039
0040     /* Enable SWAT */
0041     ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
0042     if (ret)
0043         return ret;
0044
0045     /* ab8500_sysclk2 */
0046     clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
0047         AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
0048         AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
0049     ab8500_clks[AB8500_SYSCLK_BUF2] = clk;
0050
0051     /* ab8500_sysclk3 */
0052     clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
0053         AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
0054         AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
0055     ab8500_clks[AB8500_SYSCLK_BUF3] = clk;
0056
0057     /* ab8500_sysclk4 */
0058     clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
0059         AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
0060         AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
0061     ab8500_clks[AB8500_SYSCLK_BUF4] = clk;
0062
0063     /* ab_ulpclk */
0064     clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
0065         AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
0066         AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
0067         38400000, 9000, 0);
0068     ab8500_clks[AB8500_SYSCLK_ULP] = clk;
0069
0070     /* ab8500_intclk */
0071     clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
0072         intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
0073     ab8500_clks[AB8500_SYSCLK_INT] = clk;
0074
0075     /* ab8500_audioclk */
0076     clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
0077         AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
0078         AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
0079     ab8500_clks[AB8500_SYSCLK_AUDIO] = clk;
0080
0081     ab8500_clk_data.clks = ab8500_clks;
0082     ab8500_clk_data.clk_num = ARRAY_SIZE(ab8500_clks);
0083     of_clk_add_provider(np, of_clk_src_onecell_get, &ab8500_clk_data);
0084
0085     dev_info(dev, "registered clocks for ab850x\n");
0086
0087     return 0;
0088 }
0089
0090 static int abx500_clk_probe(struct platform_device *pdev)
0091 {
0092     struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
0093     int ret;
0094
0095     if (is_ab8500(parent) || is_ab8505(parent)) {
0096         ret = ab8500_reg_clks(&pdev->dev);
0097     } else {
0098         dev_err(&pdev->dev, "non supported plf id\n");
0099         return -ENODEV;
0100     }
0101
0102     return ret;
0103 }
0104
0105 static const struct of_device_id abx500_clk_match[] = {
0106     { .compatible = "stericsson,ab8500-clk", },
0107     {}
0108 };
0109
0110 static struct platform_driver abx500_clk_driver = {
0111     .driver = {
0112         .name = "abx500-clk",
0113         .of_match_table = abx500_clk_match,
0114     },
0115     .probe  = abx500_clk_probe,
0116 };
0117
0118 static int __init abx500_clk_init(void)
0119 {
0120     return platform_driver_register(&abx500_clk_driver);
0121 }
0122 arch_initcall(abx500_clk_init);
0123
0124 MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
0125 MODULE_DESCRIPTION("ABX500 clk driver");
0126 MODULE_LICENSE("GPL v2");