clk/uniphier/clk-uniphier.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2016 Socionext Inc.
0004  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0005  */
0006
0007 #ifndef __CLK_UNIPHIER_H__
0008 #define __CLK_UNIPHIER_H__
0009
0010 struct clk_hw;
0011 struct device;
0012 struct regmap;
0013
0014 #define UNIPHIER_CLK_CPUGEAR_MAX_PARENTS    16
0015 #define UNIPHIER_CLK_MUX_MAX_PARENTS        8
0016
0017 enum uniphier_clk_type {
0018     UNIPHIER_CLK_TYPE_CPUGEAR,
0019     UNIPHIER_CLK_TYPE_FIXED_FACTOR,
0020     UNIPHIER_CLK_TYPE_FIXED_RATE,
0021     UNIPHIER_CLK_TYPE_GATE,
0022     UNIPHIER_CLK_TYPE_MUX,
0023 };
0024
0025 struct uniphier_clk_cpugear_data {
0026     const char *parent_names[UNIPHIER_CLK_CPUGEAR_MAX_PARENTS];
0027     unsigned int num_parents;
0028     unsigned int regbase;
0029     unsigned int mask;
0030 };
0031
0032 struct uniphier_clk_fixed_factor_data {
0033     const char *parent_name;
0034     unsigned int mult;
0035     unsigned int div;
0036 };
0037
0038 struct uniphier_clk_fixed_rate_data {
0039     unsigned long fixed_rate;
0040 };
0041
0042 struct uniphier_clk_gate_data {
0043     const char *parent_name;
0044     unsigned int reg;
0045     unsigned int bit;
0046 };
0047
0048 struct uniphier_clk_mux_data {
0049     const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
0050     unsigned int num_parents;
0051     unsigned int reg;
0052     unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
0053     unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
0054 };
0055
0056 struct uniphier_clk_data {
0057     const char *name;
0058     enum uniphier_clk_type type;
0059     int idx;
0060     union {
0061         struct uniphier_clk_cpugear_data cpugear;
0062         struct uniphier_clk_fixed_factor_data factor;
0063         struct uniphier_clk_fixed_rate_data rate;
0064         struct uniphier_clk_gate_data gate;
0065         struct uniphier_clk_mux_data mux;
0066     } data;
0067 };
0068
0069 #define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask,  \
0070                  _num_parents, ...)         \
0071     {                           \
0072         .name = (_name),                \
0073         .type = UNIPHIER_CLK_TYPE_CPUGEAR,      \
0074         .idx = (_idx),                  \
0075         .data.cpugear = {               \
0076             .parent_names = { __VA_ARGS__ },    \
0077             .num_parents = (_num_parents),      \
0078             .regbase = (_regbase),          \
0079             .mask = (_mask)             \
0080          },                     \
0081     }
0082
0083 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div)  \
0084     {                           \
0085         .name = (_name),                \
0086         .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,     \
0087         .idx = (_idx),                  \
0088         .data.factor = {                \
0089             .parent_name = (_parent),       \
0090             .mult = (_mult),            \
0091             .div = (_div),              \
0092         },                      \
0093     }
0094
0095 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \
0096     {                           \
0097         .name = (_name),                \
0098         .type = UNIPHIER_CLK_TYPE_GATE,         \
0099         .idx = (_idx),                  \
0100         .data.gate = {                  \
0101             .parent_name = (_parent),       \
0102             .reg = (_reg),              \
0103             .bit = (_bit),              \
0104         },                      \
0105     }
0106
0107 #define UNIPHIER_CLK_DIV(parent, div)               \
0108     UNIPHIER_CLK_FACTOR(parent "/" #div, -1, parent, 1, div)
0109
0110 #define UNIPHIER_CLK_DIV2(parent, div0, div1)           \
0111     UNIPHIER_CLK_DIV(parent, div0),             \
0112     UNIPHIER_CLK_DIV(parent, div1)
0113
0114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2)     \
0115     UNIPHIER_CLK_DIV2(parent, div0, div1),          \
0116     UNIPHIER_CLK_DIV(parent, div2)
0117
0118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3)   \
0119     UNIPHIER_CLK_DIV2(parent, div0, div1),          \
0120     UNIPHIER_CLK_DIV2(parent, div2, div3)
0121
0122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \
0123     UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3),  \
0124     UNIPHIER_CLK_DIV(parent, div4)
0125
0126 struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
0127                          struct regmap *regmap,
0128                          const char *name,
0129                 const struct uniphier_clk_cpugear_data *data);
0130 struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
0131                           const char *name,
0132             const struct uniphier_clk_fixed_factor_data *data);
0133 struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
0134                         const char *name,
0135             const struct uniphier_clk_fixed_rate_data *data);
0136 struct clk_hw *uniphier_clk_register_gate(struct device *dev,
0137                       struct regmap *regmap,
0138                       const char *name,
0139                 const struct uniphier_clk_gate_data *data);
0140 struct clk_hw *uniphier_clk_register_mux(struct device *dev,
0141                      struct regmap *regmap,
0142                      const char *name,
0143                 const struct uniphier_clk_mux_data *data);
0144
0145 extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
0146 extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
0147 extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
0148 extern const struct uniphier_clk_data uniphier_pro5_sys_clk_data[];
0149 extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
0150 extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
0151 extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
0152 extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
0153 extern const struct uniphier_clk_data uniphier_nx1_sys_clk_data[];
0154 extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
0155 extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
0156 extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
0157 extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
0158 extern const struct uniphier_clk_data uniphier_pro4_sg_clk_data[];
0159
0160 #endif /* __CLK_UNIPHIER_H__ */