clk/uniphier/clk-uniphier-cpugear.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2016 Socionext Inc.
0004  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/device.h>
0009 #include <linux/regmap.h>
0010
0011 #include "clk-uniphier.h"
0012
0013 #define UNIPHIER_CLK_CPUGEAR_STAT   0   /* status */
0014 #define UNIPHIER_CLK_CPUGEAR_SET    4   /* set */
0015 #define UNIPHIER_CLK_CPUGEAR_UPD    8   /* update */
0016 #define   UNIPHIER_CLK_CPUGEAR_UPD_BIT  BIT(0)
0017
0018 struct uniphier_clk_cpugear {
0019     struct clk_hw hw;
0020     struct regmap *regmap;
0021     unsigned int regbase;
0022     unsigned int mask;
0023 };
0024
0025 #define to_uniphier_clk_cpugear(_hw) \
0026             container_of(_hw, struct uniphier_clk_cpugear, hw)
0027
0028 static int uniphier_clk_cpugear_set_parent(struct clk_hw *hw, u8 index)
0029 {
0030     struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
0031     int ret;
0032     unsigned int val;
0033
0034     ret = regmap_write_bits(gear->regmap,
0035                 gear->regbase + UNIPHIER_CLK_CPUGEAR_SET,
0036                 gear->mask, index);
0037     if (ret)
0038         return ret;
0039
0040     ret = regmap_write_bits(gear->regmap,
0041                 gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
0042                 UNIPHIER_CLK_CPUGEAR_UPD_BIT,
0043                 UNIPHIER_CLK_CPUGEAR_UPD_BIT);
0044     if (ret)
0045         return ret;
0046
0047     return regmap_read_poll_timeout(gear->regmap,
0048                 gear->regbase + UNIPHIER_CLK_CPUGEAR_UPD,
0049                 val, !(val & UNIPHIER_CLK_CPUGEAR_UPD_BIT),
0050                 0, 1);
0051 }
0052
0053 static u8 uniphier_clk_cpugear_get_parent(struct clk_hw *hw)
0054 {
0055     struct uniphier_clk_cpugear *gear = to_uniphier_clk_cpugear(hw);
0056     int num_parents = clk_hw_get_num_parents(hw);
0057     int ret;
0058     unsigned int val;
0059
0060     ret = regmap_read(gear->regmap,
0061               gear->regbase + UNIPHIER_CLK_CPUGEAR_STAT, &val);
0062     if (ret)
0063         return ret;
0064
0065     val &= gear->mask;
0066
0067     return val < num_parents ? val : -EINVAL;
0068 }
0069
0070 static const struct clk_ops uniphier_clk_cpugear_ops = {
0071     .determine_rate = __clk_mux_determine_rate,
0072     .set_parent = uniphier_clk_cpugear_set_parent,
0073     .get_parent = uniphier_clk_cpugear_get_parent,
0074 };
0075
0076 struct clk_hw *uniphier_clk_register_cpugear(struct device *dev,
0077                      struct regmap *regmap,
0078                      const char *name,
0079                 const struct uniphier_clk_cpugear_data *data)
0080 {
0081     struct uniphier_clk_cpugear *gear;
0082     struct clk_init_data init;
0083     int ret;
0084
0085     gear = devm_kzalloc(dev, sizeof(*gear), GFP_KERNEL);
0086     if (!gear)
0087         return ERR_PTR(-ENOMEM);
0088
0089     init.name = name;
0090     init.ops = &uniphier_clk_cpugear_ops;
0091     init.flags = CLK_SET_RATE_PARENT;
0092     init.parent_names = data->parent_names;
0093     init.num_parents = data->num_parents;
0094
0095     gear->regmap = regmap;
0096     gear->regbase = data->regbase;
0097     gear->mask = data->mask;
0098     gear->hw.init = &init;
0099
0100     ret = devm_clk_hw_register(dev, &gear->hw);
0101     if (ret)
0102         return ERR_PTR(ret);
0103
0104     return &gear->hw;
0105 }