clk/ti/dpll44xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP4-specific DPLL control functions
0004  *
0005  * Copyright (C) 2011 Texas Instruments, Inc.
0006  * Rajendra Nayak
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/errno.h>
0011 #include <linux/clk.h>
0012 #include <linux/io.h>
0013 #include <linux/bitops.h>
0014 #include <linux/clk/ti.h>
0015
0016 #include "clock.h"
0017
0018 /*
0019  * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
0020  * can supported when using the DPLL low-power mode. Frequencies are
0021  * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
0022  * Status, and Low-Power Operation Mode".
0023  */
0024 #define OMAP4_DPLL_LP_FINT_MAX  1000000
0025 #define OMAP4_DPLL_LP_FOUT_MAX  100000000
0026
0027 /*
0028  * Bitfield declarations
0029  */
0030 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK     BIT(8)
0031 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK       BIT(10)
0032 #define OMAP4430_DPLL_REGM4XEN_MASK         BIT(11)
0033
0034 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
0035 #define OMAP4430_REGM4XEN_MULT              4
0036
0037 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
0038 {
0039     u32 v;
0040     u32 mask;
0041
0042     if (!clk)
0043         return;
0044
0045     mask = clk->flags & CLOCK_CLKOUTX2 ?
0046             OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
0047             OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
0048
0049     v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
0050     /* Clear the bit to allow gatectrl */
0051     v &= ~mask;
0052     ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
0053 }
0054
0055 static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
0056 {
0057     u32 v;
0058     u32 mask;
0059
0060     if (!clk)
0061         return;
0062
0063     mask = clk->flags & CLOCK_CLKOUTX2 ?
0064             OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
0065             OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
0066
0067     v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
0068     /* Set the bit to deny gatectrl */
0069     v |= mask;
0070     ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
0071 }
0072
0073 const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
0074     .allow_idle = omap4_dpllmx_allow_gatectrl,
0075     .deny_idle      = omap4_dpllmx_deny_gatectrl,
0076 };
0077
0078 /**
0079  * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
0080  * @dd: pointer to the dpll data structure
0081  *
0082  * Calculates if low-power mode can be enabled based upon the last
0083  * multiplier and divider values calculated. If low-power mode can be
0084  * enabled, then the bit to enable low-power mode is stored in the
0085  * last_rounded_lpmode variable. This implementation is based upon the
0086  * criteria for enabling low-power mode as described in the OMAP4430/60
0087  * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
0088  * Operation Mode".
0089  */
0090 static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
0091 {
0092     long fint, fout;
0093
0094     fint = clk_hw_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
0095     fout = fint * dd->last_rounded_m;
0096
0097     if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
0098         dd->last_rounded_lpmode = 1;
0099     else
0100         dd->last_rounded_lpmode = 0;
0101 }
0102
0103 /**
0104  * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
0105  * @hw: pointer to the clock to compute the rate for
0106  * @parent_rate: clock rate of the DPLL parent
0107  *
0108  * Compute the output rate for the OMAP4 DPLL represented by @clk.
0109  * Takes the REGM4XEN bit into consideration, which is needed for the
0110  * OMAP4 ABE DPLL.  Returns the DPLL's output rate (before M-dividers)
0111  * upon success, or 0 upon error.
0112  */
0113 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
0114                      unsigned long parent_rate)
0115 {
0116     struct clk_hw_omap *clk = to_clk_hw_omap(hw);
0117     u32 v;
0118     unsigned long rate;
0119     struct dpll_data *dd;
0120
0121     if (!clk || !clk->dpll_data)
0122         return 0;
0123
0124     dd = clk->dpll_data;
0125
0126     rate = omap2_get_dpll_rate(clk);
0127
0128     /* regm4xen adds a multiplier of 4 to DPLL calculations */
0129     v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
0130     if (v & OMAP4430_DPLL_REGM4XEN_MASK)
0131         rate *= OMAP4430_REGM4XEN_MULT;
0132
0133     return rate;
0134 }
0135
0136 /**
0137  * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
0138  * @hw: struct hw_clk containing the struct clk * of the DPLL to round a rate for
0139  * @target_rate: the desired rate of the DPLL
0140  * @parent_rate: clock rate of the DPLL parent
0141  *
0142  * Compute the rate that would be programmed into the DPLL hardware
0143  * for @clk if set_rate() were to be provided with the rate
0144  * @target_rate.  Takes the REGM4XEN bit into consideration, which is
0145  * needed for the OMAP4 ABE DPLL.  Returns the rounded rate (before
0146  * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
0147  * ~0 if an error occurred in omap2_dpll_round_rate().
0148  */
0149 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
0150                     unsigned long target_rate,
0151                     unsigned long *parent_rate)
0152 {
0153     struct clk_hw_omap *clk = to_clk_hw_omap(hw);
0154     struct dpll_data *dd;
0155     long r;
0156
0157     if (!clk || !clk->dpll_data)
0158         return -EINVAL;
0159
0160     dd = clk->dpll_data;
0161
0162     dd->last_rounded_m4xen = 0;
0163
0164     /*
0165      * First try to compute the DPLL configuration for
0166      * target rate without using the 4X multiplier.
0167      */
0168     r = omap2_dpll_round_rate(hw, target_rate, NULL);
0169     if (r != ~0)
0170         goto out;
0171
0172     /*
0173      * If we did not find a valid DPLL configuration, try again, but
0174      * this time see if using the 4X multiplier can help. Enabling the
0175      * 4X multiplier is equivalent to dividing the target rate by 4.
0176      */
0177     r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
0178                   NULL);
0179     if (r == ~0)
0180         return r;
0181
0182     dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
0183     dd->last_rounded_m4xen = 1;
0184
0185 out:
0186     omap4_dpll_lpmode_recalc(dd);
0187
0188     return dd->last_rounded_rate;
0189 }
0190
0191 /**
0192  * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
0193  * @hw: pointer to the clock to determine rate for
0194  * @req: target rate request
0195  *
0196  * Determines which DPLL mode to use for reaching a desired rate.
0197  * Checks whether the DPLL shall be in bypass or locked mode, and if
0198  * locked, calculates the M,N values for the DPLL via round-rate.
0199  * Returns 0 on success and a negative error value otherwise.
0200  */
0201 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
0202                        struct clk_rate_request *req)
0203 {
0204     struct clk_hw_omap *clk = to_clk_hw_omap(hw);
0205     struct dpll_data *dd;
0206
0207     if (!req->rate)
0208         return -EINVAL;
0209
0210     dd = clk->dpll_data;
0211     if (!dd)
0212         return -EINVAL;
0213
0214     if (clk_hw_get_rate(dd->clk_bypass) == req->rate &&
0215         (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
0216         req->best_parent_hw = dd->clk_bypass;
0217     } else {
0218         req->rate = omap4_dpll_regm4xen_round_rate(hw, req->rate,
0219                         &req->best_parent_rate);
0220         req->best_parent_hw = dd->clk_ref;
0221     }
0222
0223     req->best_parent_rate = req->rate;
0224
0225     return 0;
0226 }