clk/ti/dpll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP DPLL clock support
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  *
0007  * Tero Kristo <t-kristo@ti.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/slab.h>
0013 #include <linux/err.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/clk/ti.h>
0017 #include "clock.h"
0018
0019 #undef pr_fmt
0020 #define pr_fmt(fmt) "%s: " fmt, __func__
0021
0022 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
0023     defined(CONFIG_SOC_DRA7XX)
0024 static const struct clk_ops dpll_m4xen_ck_ops = {
0025     .enable     = &omap3_noncore_dpll_enable,
0026     .disable    = &omap3_noncore_dpll_disable,
0027     .recalc_rate    = &omap4_dpll_regm4xen_recalc,
0028     .round_rate = &omap4_dpll_regm4xen_round_rate,
0029     .set_rate   = &omap3_noncore_dpll_set_rate,
0030     .set_parent = &omap3_noncore_dpll_set_parent,
0031     .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
0032     .determine_rate = &omap4_dpll_regm4xen_determine_rate,
0033     .get_parent = &omap2_init_dpll_parent,
0034     .save_context   = &omap3_core_dpll_save_context,
0035     .restore_context = &omap3_core_dpll_restore_context,
0036 };
0037 #else
0038 static const struct clk_ops dpll_m4xen_ck_ops = {};
0039 #endif
0040
0041 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
0042     defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
0043     defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
0044 static const struct clk_ops dpll_core_ck_ops = {
0045     .recalc_rate    = &omap3_dpll_recalc,
0046     .get_parent = &omap2_init_dpll_parent,
0047 };
0048
0049 static const struct clk_ops dpll_ck_ops = {
0050     .enable     = &omap3_noncore_dpll_enable,
0051     .disable    = &omap3_noncore_dpll_disable,
0052     .recalc_rate    = &omap3_dpll_recalc,
0053     .round_rate = &omap2_dpll_round_rate,
0054     .set_rate   = &omap3_noncore_dpll_set_rate,
0055     .set_parent = &omap3_noncore_dpll_set_parent,
0056     .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
0057     .determine_rate = &omap3_noncore_dpll_determine_rate,
0058     .get_parent = &omap2_init_dpll_parent,
0059     .save_context   = &omap3_noncore_dpll_save_context,
0060     .restore_context = &omap3_noncore_dpll_restore_context,
0061 };
0062
0063 static const struct clk_ops dpll_no_gate_ck_ops = {
0064     .recalc_rate    = &omap3_dpll_recalc,
0065     .get_parent = &omap2_init_dpll_parent,
0066     .round_rate = &omap2_dpll_round_rate,
0067     .set_rate   = &omap3_noncore_dpll_set_rate,
0068     .set_parent = &omap3_noncore_dpll_set_parent,
0069     .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
0070     .determine_rate = &omap3_noncore_dpll_determine_rate,
0071     .save_context   = &omap3_noncore_dpll_save_context,
0072     .restore_context = &omap3_noncore_dpll_restore_context
0073 };
0074 #else
0075 static const struct clk_ops dpll_core_ck_ops = {};
0076 static const struct clk_ops dpll_ck_ops = {};
0077 static const struct clk_ops dpll_no_gate_ck_ops = {};
0078 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
0079 #endif
0080
0081 #ifdef CONFIG_ARCH_OMAP2
0082 static const struct clk_ops omap2_dpll_core_ck_ops = {
0083     .get_parent = &omap2_init_dpll_parent,
0084     .recalc_rate    = &omap2_dpllcore_recalc,
0085     .round_rate = &omap2_dpll_round_rate,
0086     .set_rate   = &omap2_reprogram_dpllcore,
0087 };
0088 #else
0089 static const struct clk_ops omap2_dpll_core_ck_ops = {};
0090 #endif
0091
0092 #ifdef CONFIG_ARCH_OMAP3
0093 static const struct clk_ops omap3_dpll_core_ck_ops = {
0094     .get_parent = &omap2_init_dpll_parent,
0095     .recalc_rate    = &omap3_dpll_recalc,
0096     .round_rate = &omap2_dpll_round_rate,
0097 };
0098 #else
0099 static const struct clk_ops omap3_dpll_core_ck_ops = {};
0100 #endif
0101
0102 #ifdef CONFIG_ARCH_OMAP3
0103 static const struct clk_ops omap3_dpll_ck_ops = {
0104     .enable     = &omap3_noncore_dpll_enable,
0105     .disable    = &omap3_noncore_dpll_disable,
0106     .get_parent = &omap2_init_dpll_parent,
0107     .recalc_rate    = &omap3_dpll_recalc,
0108     .set_rate   = &omap3_noncore_dpll_set_rate,
0109     .set_parent = &omap3_noncore_dpll_set_parent,
0110     .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
0111     .determine_rate = &omap3_noncore_dpll_determine_rate,
0112     .round_rate = &omap2_dpll_round_rate,
0113 };
0114
0115 static const struct clk_ops omap3_dpll5_ck_ops = {
0116     .enable     = &omap3_noncore_dpll_enable,
0117     .disable    = &omap3_noncore_dpll_disable,
0118     .get_parent = &omap2_init_dpll_parent,
0119     .recalc_rate    = &omap3_dpll_recalc,
0120     .set_rate   = &omap3_dpll5_set_rate,
0121     .set_parent = &omap3_noncore_dpll_set_parent,
0122     .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
0123     .determine_rate = &omap3_noncore_dpll_determine_rate,
0124     .round_rate = &omap2_dpll_round_rate,
0125 };
0126
0127 static const struct clk_ops omap3_dpll_per_ck_ops = {
0128     .enable     = &omap3_noncore_dpll_enable,
0129     .disable    = &omap3_noncore_dpll_disable,
0130     .get_parent = &omap2_init_dpll_parent,
0131     .recalc_rate    = &omap3_dpll_recalc,
0132     .set_rate   = &omap3_dpll4_set_rate,
0133     .set_parent = &omap3_noncore_dpll_set_parent,
0134     .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
0135     .determine_rate = &omap3_noncore_dpll_determine_rate,
0136     .round_rate = &omap2_dpll_round_rate,
0137 };
0138 #endif
0139
0140 static const struct clk_ops dpll_x2_ck_ops = {
0141     .recalc_rate    = &omap3_clkoutx2_recalc,
0142 };
0143
0144 /**
0145  * _register_dpll - low level registration of a DPLL clock
0146  * @user: pointer to the hardware clock definition for the clock
0147  * @node: device node for the clock
0148  *
0149  * Finalizes DPLL registration process. In case a failure (clk-ref or
0150  * clk-bypass is missing), the clock is added to retry list and
0151  * the initialization is retried on later stage.
0152  */
0153 static void __init _register_dpll(void *user,
0154                   struct device_node *node)
0155 {
0156     struct clk_hw *hw = user;
0157     struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
0158     struct dpll_data *dd = clk_hw->dpll_data;
0159     const char *name;
0160     struct clk *clk;
0161     const struct clk_init_data *init = hw->init;
0162
0163     clk = of_clk_get(node, 0);
0164     if (IS_ERR(clk)) {
0165         pr_debug("clk-ref missing for %pOFn, retry later\n",
0166              node);
0167         if (!ti_clk_retry_init(node, hw, _register_dpll))
0168             return;
0169
0170         goto cleanup;
0171     }
0172
0173     dd->clk_ref = __clk_get_hw(clk);
0174
0175     clk = of_clk_get(node, 1);
0176
0177     if (IS_ERR(clk)) {
0178         pr_debug("clk-bypass missing for %pOFn, retry later\n",
0179              node);
0180         if (!ti_clk_retry_init(node, hw, _register_dpll))
0181             return;
0182
0183         goto cleanup;
0184     }
0185
0186     dd->clk_bypass = __clk_get_hw(clk);
0187
0188     /* register the clock */
0189     name = ti_dt_clk_name(node);
0190     clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
0191
0192     if (!IS_ERR(clk)) {
0193         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0194         kfree(init->parent_names);
0195         kfree(init);
0196         return;
0197     }
0198
0199 cleanup:
0200     kfree(clk_hw->dpll_data);
0201     kfree(init->parent_names);
0202     kfree(init);
0203     kfree(clk_hw);
0204 }
0205
0206 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
0207     defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
0208     defined(CONFIG_SOC_AM43XX)
0209 /**
0210  * _register_dpll_x2 - Registers a DPLLx2 clock
0211  * @node: device node for this clock
0212  * @ops: clk_ops for this clock
0213  * @hw_ops: clk_hw_ops for this clock
0214  *
0215  * Initializes a DPLL x 2 clock from device tree data.
0216  */
0217 static void _register_dpll_x2(struct device_node *node,
0218                   const struct clk_ops *ops,
0219                   const struct clk_hw_omap_ops *hw_ops)
0220 {
0221     struct clk *clk;
0222     struct clk_init_data init = { NULL };
0223     struct clk_hw_omap *clk_hw;
0224     const char *name = ti_dt_clk_name(node);
0225     const char *parent_name;
0226
0227     parent_name = of_clk_get_parent_name(node, 0);
0228     if (!parent_name) {
0229         pr_err("%pOFn must have parent\n", node);
0230         return;
0231     }
0232
0233     clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
0234     if (!clk_hw)
0235         return;
0236
0237     clk_hw->ops = hw_ops;
0238     clk_hw->hw.init = &init;
0239
0240     init.name = name;
0241     init.ops = ops;
0242     init.parent_names = &parent_name;
0243     init.num_parents = 1;
0244
0245 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
0246     defined(CONFIG_SOC_DRA7XX)
0247     if (hw_ops == &clkhwops_omap4_dpllmx) {
0248         int ret;
0249
0250         /* Check if register defined, if not, drop hw-ops */
0251         ret = of_property_count_elems_of_size(node, "reg", 1);
0252         if (ret <= 0) {
0253             clk_hw->ops = NULL;
0254         } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
0255             kfree(clk_hw);
0256             return;
0257         }
0258     }
0259 #endif
0260
0261     /* register the clock */
0262     clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
0263
0264     if (IS_ERR(clk))
0265         kfree(clk_hw);
0266     else
0267         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0268 }
0269 #endif
0270
0271 /**
0272  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
0273  * @node: device node containing the DPLL info
0274  * @ops: ops for the DPLL
0275  * @ddt: DPLL data template to use
0276  *
0277  * Initializes a DPLL clock from device tree data.
0278  */
0279 static void __init of_ti_dpll_setup(struct device_node *node,
0280                     const struct clk_ops *ops,
0281                     const struct dpll_data *ddt)
0282 {
0283     struct clk_hw_omap *clk_hw = NULL;
0284     struct clk_init_data *init = NULL;
0285     const char **parent_names = NULL;
0286     struct dpll_data *dd = NULL;
0287     int ssc_clk_index;
0288     u8 dpll_mode = 0;
0289     u32 min_div;
0290
0291     dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
0292     clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
0293     init = kzalloc(sizeof(*init), GFP_KERNEL);
0294     if (!dd || !clk_hw || !init)
0295         goto cleanup;
0296
0297     clk_hw->dpll_data = dd;
0298     clk_hw->ops = &clkhwops_omap3_dpll;
0299     clk_hw->hw.init = init;
0300
0301     init->name = ti_dt_clk_name(node);
0302     init->ops = ops;
0303
0304     init->num_parents = of_clk_get_parent_count(node);
0305     if (!init->num_parents) {
0306         pr_err("%pOFn must have parent(s)\n", node);
0307         goto cleanup;
0308     }
0309
0310     parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
0311     if (!parent_names)
0312         goto cleanup;
0313
0314     of_clk_parent_fill(node, parent_names, init->num_parents);
0315
0316     init->parent_names = parent_names;
0317
0318     if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
0319         goto cleanup;
0320
0321     /*
0322      * Special case for OMAP2 DPLL, register order is different due to
0323      * missing idlest_reg, also clkhwops is different. Detected from
0324      * missing idlest_mask.
0325      */
0326     if (!dd->idlest_mask) {
0327         if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
0328             goto cleanup;
0329 #ifdef CONFIG_ARCH_OMAP2
0330         clk_hw->ops = &clkhwops_omap2xxx_dpll;
0331         omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
0332 #endif
0333     } else {
0334         if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
0335             goto cleanup;
0336
0337         if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
0338             goto cleanup;
0339     }
0340
0341     if (dd->autoidle_mask) {
0342         if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
0343             goto cleanup;
0344
0345         ssc_clk_index = 4;
0346     } else {
0347         ssc_clk_index = 3;
0348     }
0349
0350     if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&
0351         dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {
0352         if (ti_clk_get_reg_addr(node, ssc_clk_index++,
0353                     &dd->ssc_deltam_reg))
0354             goto cleanup;
0355
0356         if (ti_clk_get_reg_addr(node, ssc_clk_index++,
0357                     &dd->ssc_modfreq_reg))
0358             goto cleanup;
0359
0360         of_property_read_u32(node, "ti,ssc-modfreq-hz",
0361                      &dd->ssc_modfreq);
0362         of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);
0363         dd->ssc_downspread =
0364             of_property_read_bool(node, "ti,ssc-downspread");
0365     }
0366
0367     if (of_property_read_bool(node, "ti,low-power-stop"))
0368         dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
0369
0370     if (of_property_read_bool(node, "ti,low-power-bypass"))
0371         dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
0372
0373     if (of_property_read_bool(node, "ti,lock"))
0374         dpll_mode |= 1 << DPLL_LOCKED;
0375
0376     if (!of_property_read_u32(node, "ti,min-div", &min_div) &&
0377         min_div > dd->min_divider)
0378         dd->min_divider = min_div;
0379
0380     if (dpll_mode)
0381         dd->modes = dpll_mode;
0382
0383     _register_dpll(&clk_hw->hw, node);
0384     return;
0385
0386 cleanup:
0387     kfree(dd);
0388     kfree(parent_names);
0389     kfree(init);
0390     kfree(clk_hw);
0391 }
0392
0393 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
0394     defined(CONFIG_SOC_DRA7XX)
0395 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
0396 {
0397     _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
0398 }
0399 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
0400            of_ti_omap4_dpll_x2_setup);
0401 #endif
0402
0403 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
0404 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
0405 {
0406     _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
0407 }
0408 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
0409            of_ti_am3_dpll_x2_setup);
0410 #endif
0411
0412 #ifdef CONFIG_ARCH_OMAP3
0413 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
0414 {
0415     const struct dpll_data dd = {
0416         .idlest_mask = 0x1,
0417         .enable_mask = 0x7,
0418         .autoidle_mask = 0x7,
0419         .mult_mask = 0x7ff << 8,
0420         .div1_mask = 0x7f,
0421         .max_multiplier = 2047,
0422         .max_divider = 128,
0423         .min_divider = 1,
0424         .freqsel_mask = 0xf0,
0425         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0426     };
0427
0428     if ((of_machine_is_compatible("ti,omap3630") ||
0429          of_machine_is_compatible("ti,omap36xx")) &&
0430          of_node_name_eq(node, "dpll5_ck"))
0431         of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
0432     else
0433         of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
0434 }
0435 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
0436            of_ti_omap3_dpll_setup);
0437
0438 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
0439 {
0440     const struct dpll_data dd = {
0441         .idlest_mask = 0x1,
0442         .enable_mask = 0x7,
0443         .autoidle_mask = 0x7,
0444         .mult_mask = 0x7ff << 16,
0445         .div1_mask = 0x7f << 8,
0446         .max_multiplier = 2047,
0447         .max_divider = 128,
0448         .min_divider = 1,
0449         .freqsel_mask = 0xf0,
0450     };
0451
0452     of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
0453 }
0454 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
0455            of_ti_omap3_core_dpll_setup);
0456
0457 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
0458 {
0459     const struct dpll_data dd = {
0460         .idlest_mask = 0x1 << 1,
0461         .enable_mask = 0x7 << 16,
0462         .autoidle_mask = 0x7 << 3,
0463         .mult_mask = 0x7ff << 8,
0464         .div1_mask = 0x7f,
0465         .max_multiplier = 2047,
0466         .max_divider = 128,
0467         .min_divider = 1,
0468         .freqsel_mask = 0xf00000,
0469         .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
0470     };
0471
0472     of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
0473 }
0474 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
0475            of_ti_omap3_per_dpll_setup);
0476
0477 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
0478 {
0479     const struct dpll_data dd = {
0480         .idlest_mask = 0x1 << 1,
0481         .enable_mask = 0x7 << 16,
0482         .autoidle_mask = 0x7 << 3,
0483         .mult_mask = 0xfff << 8,
0484         .div1_mask = 0x7f,
0485         .max_multiplier = 4095,
0486         .max_divider = 128,
0487         .min_divider = 1,
0488         .sddiv_mask = 0xff << 24,
0489         .dco_mask = 0xe << 20,
0490         .flags = DPLL_J_TYPE,
0491         .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
0492     };
0493
0494     of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
0495 }
0496 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
0497            of_ti_omap3_per_jtype_dpll_setup);
0498 #endif
0499
0500 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
0501 {
0502     const struct dpll_data dd = {
0503         .idlest_mask = 0x1,
0504         .enable_mask = 0x7,
0505         .autoidle_mask = 0x7,
0506         .mult_mask = 0x7ff << 8,
0507         .div1_mask = 0x7f,
0508         .max_multiplier = 2047,
0509         .max_divider = 128,
0510         .min_divider = 1,
0511         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0512     };
0513
0514     of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
0515 }
0516 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
0517            of_ti_omap4_dpll_setup);
0518
0519 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
0520 {
0521     const struct dpll_data dd = {
0522         .idlest_mask = 0x1,
0523         .enable_mask = 0x7,
0524         .autoidle_mask = 0x7,
0525         .mult_mask = 0x7ff << 8,
0526         .div1_mask = 0x7f,
0527         .max_multiplier = 2047,
0528         .max_divider = 128,
0529         .dcc_mask = BIT(22),
0530         .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
0531         .min_divider = 1,
0532         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0533     };
0534
0535     of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
0536 }
0537 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
0538            of_ti_omap5_mpu_dpll_setup);
0539
0540 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
0541 {
0542     const struct dpll_data dd = {
0543         .idlest_mask = 0x1,
0544         .enable_mask = 0x7,
0545         .autoidle_mask = 0x7,
0546         .mult_mask = 0x7ff << 8,
0547         .div1_mask = 0x7f,
0548         .max_multiplier = 2047,
0549         .max_divider = 128,
0550         .min_divider = 1,
0551         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0552     };
0553
0554     of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
0555 }
0556 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
0557            of_ti_omap4_core_dpll_setup);
0558
0559 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
0560     defined(CONFIG_SOC_DRA7XX)
0561 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
0562 {
0563     const struct dpll_data dd = {
0564         .idlest_mask = 0x1,
0565         .enable_mask = 0x7,
0566         .autoidle_mask = 0x7,
0567         .mult_mask = 0x7ff << 8,
0568         .div1_mask = 0x7f,
0569         .max_multiplier = 2047,
0570         .max_divider = 128,
0571         .min_divider = 1,
0572         .m4xen_mask = 0x800,
0573         .lpmode_mask = 1 << 10,
0574         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0575     };
0576
0577     of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
0578 }
0579 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
0580            of_ti_omap4_m4xen_dpll_setup);
0581
0582 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
0583 {
0584     const struct dpll_data dd = {
0585         .idlest_mask = 0x1,
0586         .enable_mask = 0x7,
0587         .autoidle_mask = 0x7,
0588         .mult_mask = 0xfff << 8,
0589         .div1_mask = 0xff,
0590         .max_multiplier = 4095,
0591         .max_divider = 256,
0592         .min_divider = 1,
0593         .sddiv_mask = 0xff << 24,
0594         .flags = DPLL_J_TYPE,
0595         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0596     };
0597
0598     of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
0599 }
0600 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
0601            of_ti_omap4_jtype_dpll_setup);
0602 #endif
0603
0604 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
0605 {
0606     const struct dpll_data dd = {
0607         .idlest_mask = 0x1,
0608         .enable_mask = 0x7,
0609         .ssc_enable_mask = 0x1 << 12,
0610         .ssc_downspread_mask = 0x1 << 14,
0611         .mult_mask = 0x7ff << 8,
0612         .div1_mask = 0x7f,
0613         .ssc_deltam_int_mask = 0x3 << 18,
0614         .ssc_deltam_frac_mask = 0x3ffff,
0615         .ssc_modfreq_mant_mask = 0x7f,
0616         .ssc_modfreq_exp_mask = 0x7 << 8,
0617         .max_multiplier = 2047,
0618         .max_divider = 128,
0619         .min_divider = 1,
0620         .max_rate = 1000000000,
0621         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0622     };
0623
0624     of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
0625 }
0626 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
0627            of_ti_am3_no_gate_dpll_setup);
0628
0629 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
0630 {
0631     const struct dpll_data dd = {
0632         .idlest_mask = 0x1,
0633         .enable_mask = 0x7,
0634         .mult_mask = 0x7ff << 8,
0635         .div1_mask = 0x7f,
0636         .max_multiplier = 4095,
0637         .max_divider = 256,
0638         .min_divider = 2,
0639         .flags = DPLL_J_TYPE,
0640         .max_rate = 2000000000,
0641         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0642     };
0643
0644     of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
0645 }
0646 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
0647            of_ti_am3_jtype_dpll_setup);
0648
0649 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
0650 {
0651     const struct dpll_data dd = {
0652         .idlest_mask = 0x1,
0653         .enable_mask = 0x7,
0654         .mult_mask = 0x7ff << 8,
0655         .div1_mask = 0x7f,
0656         .max_multiplier = 2047,
0657         .max_divider = 128,
0658         .min_divider = 1,
0659         .max_rate = 2000000000,
0660         .flags = DPLL_J_TYPE,
0661         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0662     };
0663
0664     of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
0665 }
0666 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
0667            "ti,am3-dpll-no-gate-j-type-clock",
0668            of_ti_am3_no_gate_jtype_dpll_setup);
0669
0670 static void __init of_ti_am3_dpll_setup(struct device_node *node)
0671 {
0672     const struct dpll_data dd = {
0673         .idlest_mask = 0x1,
0674         .enable_mask = 0x7,
0675         .ssc_enable_mask = 0x1 << 12,
0676         .ssc_downspread_mask = 0x1 << 14,
0677         .mult_mask = 0x7ff << 8,
0678         .div1_mask = 0x7f,
0679         .ssc_deltam_int_mask = 0x3 << 18,
0680         .ssc_deltam_frac_mask = 0x3ffff,
0681         .ssc_modfreq_mant_mask = 0x7f,
0682         .ssc_modfreq_exp_mask = 0x7 << 8,
0683         .max_multiplier = 2047,
0684         .max_divider = 128,
0685         .min_divider = 1,
0686         .max_rate = 1000000000,
0687         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0688     };
0689
0690     of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
0691 }
0692 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
0693
0694 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
0695 {
0696     const struct dpll_data dd = {
0697         .idlest_mask = 0x1,
0698         .enable_mask = 0x7,
0699         .mult_mask = 0x7ff << 8,
0700         .div1_mask = 0x7f,
0701         .max_multiplier = 2047,
0702         .max_divider = 128,
0703         .min_divider = 1,
0704         .max_rate = 1000000000,
0705         .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
0706     };
0707
0708     of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
0709 }
0710 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
0711            of_ti_am3_core_dpll_setup);
0712
0713 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
0714 {
0715     const struct dpll_data dd = {
0716         .enable_mask = 0x3,
0717         .mult_mask = 0x3ff << 12,
0718         .div1_mask = 0xf << 8,
0719         .max_divider = 16,
0720         .min_divider = 1,
0721     };
0722
0723     of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
0724 }
0725 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
0726            of_ti_omap2_core_dpll_setup);