clk/ti/clk-816x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 #include <linux/kernel.h>
0004 #include <linux/list.h>
0005 #include <linux/clk-provider.h>
0006 #include <linux/clk/ti.h>
0007 #include <dt-bindings/clock/dm816.h>
0008
0009 #include "clock.h"
0010
0011 static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
0012     { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0013     { 0 },
0014 };
0015
0016 static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
0017     { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0018     { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0019     { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0020     { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0021     { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0022     { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0023     { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0024     { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
0025     { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
0026     { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
0027     { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
0028     { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
0029     { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
0030     { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
0031     { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
0032     { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0033     { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0034     { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0035     { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0036     { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0037     { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
0038     { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
0039     { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
0040     { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
0041     { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0042     { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0043     { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0044     { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0045     { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0046     { 0 },
0047 };
0048
0049 const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
0050     { 0x48180500, dm816_default_clkctrl_regs },
0051     { 0x48181400, dm816_alwon_clkctrl_regs },
0052     { 0 },
0053 };
0054
0055 static struct ti_dt_clk dm816x_clks[] = {
0056     DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
0057     DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
0058     DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
0059     DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
0060     { .node_name = NULL },
0061 };
0062
0063 static const char *enable_init_clks[] = {
0064     "ddr_pll_clk1",
0065     "ddr_pll_clk2",
0066     "ddr_pll_clk3",
0067     "sysclk6_ck",
0068 };
0069
0070 int __init dm816x_dt_clk_init(void)
0071 {
0072     ti_dt_clocks_register(dm816x_clks);
0073     omap2_clk_disable_autoidle_all();
0074     ti_clk_add_aliases();
0075     omap2_clk_enable_init_clocks(enable_init_clks,
0076                      ARRAY_SIZE(enable_init_clks));
0077
0078     return 0;
0079 }