clk/ti/clk-814x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002
0003 #include <linux/kernel.h>
0004 #include <linux/clk.h>
0005 #include <linux/clk-provider.h>
0006 #include <linux/clk/ti.h>
0007 #include <linux/of_platform.h>
0008 #include <dt-bindings/clock/dm814.h>
0009
0010 #include "clock.h"
0011
0012 static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
0013     { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
0014     { 0 },
0015 };
0016
0017 static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
0018     { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0019     { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0020     { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0021     { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0022     { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0023     { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0024     { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0025     { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
0026     { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
0027     { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
0028     { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
0029     { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
0030     { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0031     { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0032     { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0033     { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0034     { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
0035     { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
0036     { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
0037     { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
0038     { 0 },
0039 };
0040
0041 static const struct
0042 omap_clkctrl_reg_data dm814_alwon_ethernet_clkctrl_regs[] __initconst = {
0043     { 0, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
0044 };
0045
0046 const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
0047     { 0x48180500, dm814_default_clkctrl_regs },
0048     { 0x48181400, dm814_alwon_clkctrl_regs },
0049     { 0x481815d4, dm814_alwon_ethernet_clkctrl_regs },
0050     { 0 },
0051 };
0052
0053 static struct ti_dt_clk dm814_clks[] = {
0054     DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
0055     { .node_name = NULL },
0056 };
0057
0058 static bool timer_clocks_initialized;
0059
0060 static int __init dm814x_adpll_early_init(void)
0061 {
0062     struct device_node *np;
0063
0064     if (!timer_clocks_initialized)
0065         return -ENODEV;
0066
0067     np = of_find_node_by_name(NULL, "pllss");
0068     if (!np) {
0069         pr_err("Could not find node for plls\n");
0070         return -ENODEV;
0071     }
0072
0073     of_platform_populate(np, NULL, NULL, NULL);
0074     of_node_put(np);
0075
0076     return 0;
0077 }
0078 core_initcall(dm814x_adpll_early_init);
0079
0080 static const char * const init_clocks[] = {
0081     "pll040clkout",     /* MPU 481c5040.adpll.clkout */
0082     "pll290clkout",     /* DDR 481c5290.adpll.clkout */
0083 };
0084
0085 static int __init dm814x_adpll_enable_init_clocks(void)
0086 {
0087     int i, err;
0088
0089     if (!timer_clocks_initialized)
0090         return -ENODEV;
0091
0092     for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
0093         struct clk *clock;
0094
0095         clock = clk_get(NULL, init_clocks[i]);
0096         if (WARN(IS_ERR(clock), "could not find init clock %s\n",
0097              init_clocks[i]))
0098             continue;
0099         err = clk_prepare_enable(clock);
0100         if (WARN(err, "could not enable init clock %s\n",
0101              init_clocks[i]))
0102             continue;
0103     }
0104
0105     return 0;
0106 }
0107 postcore_initcall(dm814x_adpll_enable_init_clocks);
0108
0109 int __init dm814x_dt_clk_init(void)
0110 {
0111     ti_dt_clocks_register(dm814_clks);
0112     omap2_clk_disable_autoidle_all();
0113     ti_clk_add_aliases();
0114     omap2_clk_enable_init_clocks(NULL, 0);
0115     timer_clocks_initialized = true;
0116
0117     return 0;
0118 }