clk/ti/clk-7xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DRA7 Clock init
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  *
0007  * Tero Kristo (t-kristo@ti.com)
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/list.h>
0012 #include <linux/clk.h>
0013 #include <linux/clkdev.h>
0014 #include <linux/clk/ti.h>
0015 #include <dt-bindings/clock/dra7.h>
0016
0017 #include "clock.h"
0018
0019 #define DRA7_DPLL_GMAC_DEFFREQ              1000000000
0020 #define DRA7_DPLL_USB_DEFFREQ               960000000
0021
0022 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
0023     { DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
0024     { 0 },
0025 };
0026
0027 static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
0028     { DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
0029     { 0 },
0030 };
0031
0032 static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
0033     "dpll_abe_m2x2_ck",
0034     "dpll_core_h22x2_ck",
0035     NULL,
0036 };
0037
0038 static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
0039     { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
0040     { 0 },
0041 };
0042
0043 static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
0044     { DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
0045     { 0 },
0046 };
0047
0048 static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
0049     "per_abe_x1_gfclk2_div",
0050     "video1_clk2_div",
0051     "video2_clk2_div",
0052     "hdmi_clk2_div",
0053     NULL,
0054 };
0055
0056 static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
0057     "abe_24m_fclk",
0058     "abe_sys_clk_div",
0059     "func_24m_clk",
0060     "atl_clkin3_ck",
0061     "atl_clkin2_ck",
0062     "atl_clkin1_ck",
0063     "atl_clkin0_ck",
0064     "sys_clkin2",
0065     "ref_clkin0_ck",
0066     "ref_clkin1_ck",
0067     "ref_clkin2_ck",
0068     "ref_clkin3_ck",
0069     "mlb_clk",
0070     "mlbp_clk",
0071     NULL,
0072 };
0073
0074 static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
0075     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0076     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0077     { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0078     { 0 },
0079 };
0080
0081 static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
0082     "timer_sys_clk_div",
0083     "sys_32k_ck",
0084     "sys_clkin2",
0085     "ref_clkin0_ck",
0086     "ref_clkin1_ck",
0087     "ref_clkin2_ck",
0088     "ref_clkin3_ck",
0089     "abe_giclk_div",
0090     "video1_div_clk",
0091     "video2_div_clk",
0092     "hdmi_div_clk",
0093     "clkoutmux0_clk_mux",
0094     NULL,
0095 };
0096
0097 static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
0098     { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
0099     { 0 },
0100 };
0101
0102 static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
0103     { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
0104     { 0 },
0105 };
0106
0107 static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
0108     { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
0109     { 0 },
0110 };
0111
0112 static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
0113     { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
0114     { 0 },
0115 };
0116
0117 static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
0118     "func_48m_fclk",
0119     "dpll_per_m2x2_ck",
0120     NULL,
0121 };
0122
0123 static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
0124     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0125     { 0 },
0126 };
0127
0128 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
0129     { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
0130     { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
0131     { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
0132     { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
0133     { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
0134     { DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0135     { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
0136     { 0 },
0137 };
0138
0139 static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
0140     { DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
0141     { 0 },
0142 };
0143
0144 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
0145     { DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0146     { 0 },
0147 };
0148
0149 static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
0150     "l3_iclk_div",
0151     "core_iss_main_clk",
0152     NULL,
0153 };
0154
0155 static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
0156     { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
0157     { 0 },
0158 };
0159
0160 static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
0161     { DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0162     { DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0163     { DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0164     { 0 },
0165 };
0166
0167 static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
0168     { DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
0169     { 0 },
0170 };
0171
0172 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
0173     { DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
0174     { DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
0175     { 0 },
0176 };
0177
0178 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
0179     { DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
0180     { DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0181     { DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
0182     { DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0183     { DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0184     { DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
0185     { DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
0186     { 0 },
0187 };
0188
0189 static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
0190     { DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
0191     { 0 },
0192 };
0193
0194 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
0195     { DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
0196     { 0 },
0197 };
0198
0199 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
0200     { DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
0201     { 0 },
0202 };
0203
0204 static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
0205     "sys_32k_ck",
0206     "video1_clkin_ck",
0207     "video2_clkin_ck",
0208     "hdmi_clkin_ck",
0209     NULL,
0210 };
0211
0212 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
0213     "l3_iclk_div",
0214     "dpll_abe_m2_ck",
0215     "atl-clkctrl:0000:24",
0216     NULL,
0217 };
0218
0219 static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
0220     { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
0221     { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
0222     { 0 },
0223 };
0224
0225 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
0226     { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
0227     { 0 },
0228 };
0229
0230 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
0231     { DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
0232     { DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
0233     { DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
0234     { DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
0235     { DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
0236     { DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
0237     { DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
0238     { DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
0239     { DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
0240     { DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
0241     { DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
0242     { DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
0243     { DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
0244     { DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
0245     { DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
0246     { 0 },
0247 };
0248
0249 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
0250     { DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0251     { DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0252     { 0 },
0253 };
0254
0255 static const struct omap_clkctrl_reg_data dra7_iva_clkctrl_regs[] __initconst = {
0256     { DRA7_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h12x2_ck" },
0257     { DRA7_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
0258     { 0 },
0259 };
0260
0261 static const char * const dra7_dss_dss_clk_parents[] __initconst = {
0262     "dpll_per_h12x2_ck",
0263     NULL,
0264 };
0265
0266 static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
0267     "func_48m_fclk",
0268     NULL,
0269 };
0270
0271 static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
0272     "hdmi_dpll_clk_mux",
0273     NULL,
0274 };
0275
0276 static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
0277     "sys_32k_ck",
0278     NULL,
0279 };
0280
0281 static const char * const dra7_dss_video1_clk_parents[] __initconst = {
0282     "video1_dpll_clk_mux",
0283     NULL,
0284 };
0285
0286 static const char * const dra7_dss_video2_clk_parents[] __initconst = {
0287     "video2_dpll_clk_mux",
0288     NULL,
0289 };
0290
0291 static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
0292     { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
0293     { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
0294     { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
0295     { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0296     { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
0297     { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
0298     { 0 },
0299 };
0300
0301 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
0302     { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
0303     { DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
0304     { 0 },
0305 };
0306
0307 static const char * const dra7_gpu_core_mux_parents[] __initconst = {
0308     "dpll_core_h14x2_ck",
0309     "dpll_per_h14x2_ck",
0310     "dpll_gpu_m2_ck",
0311     NULL,
0312 };
0313
0314 static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
0315     "dpll_core_h14x2_ck",
0316     "dpll_per_h14x2_ck",
0317     "dpll_gpu_m2_ck",
0318     NULL,
0319 };
0320
0321 static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
0322     { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
0323     { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
0324     { 0 },
0325 };
0326
0327 static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
0328     { DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },
0329     { 0 },
0330 };
0331
0332 static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
0333     "func_128m_clk",
0334     "dpll_per_m2x2_ck",
0335     NULL,
0336 };
0337
0338 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
0339     "l3init-clkctrl:0008:24",
0340     NULL,
0341 };
0342
0343 static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
0344     .max_div = 4,
0345     .flags = CLK_DIVIDER_POWER_OF_TWO,
0346 };
0347
0348 static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
0349     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0350     { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
0351     { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
0352     { 0 },
0353 };
0354
0355 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
0356     "l3init-clkctrl:0010:24",
0357     NULL,
0358 };
0359
0360 static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
0361     .max_div = 4,
0362     .flags = CLK_DIVIDER_POWER_OF_TWO,
0363 };
0364
0365 static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
0366     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0367     { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
0368     { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
0369     { 0 },
0370 };
0371
0372 static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
0373     "l3init_960m_gfclk",
0374     NULL,
0375 };
0376
0377 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
0378     { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
0379     { 0 },
0380 };
0381
0382 static const char * const dra7_sata_ref_clk_parents[] __initconst = {
0383     "sys_clkin1",
0384     NULL,
0385 };
0386
0387 static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
0388     { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
0389     { 0 },
0390 };
0391
0392 static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
0393     { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
0394     { 0 },
0395 };
0396
0397 static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
0398     { DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
0399     { DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
0400     { DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
0401     { DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
0402     { DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
0403     { DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
0404     { DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
0405     { DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
0406     { DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
0407     { 0 },
0408 };
0409
0410 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
0411     "apll_pcie_ck",
0412     NULL,
0413 };
0414
0415 static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
0416     "optfclk_pciephy_div",
0417     NULL,
0418 };
0419
0420 static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
0421     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0422     { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
0423     { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
0424     { 0 },
0425 };
0426
0427 static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
0428     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0429     { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
0430     { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
0431     { 0 },
0432 };
0433
0434 static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
0435     { DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
0436     { DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
0437     { 0 },
0438 };
0439
0440 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
0441     "dpll_gmac_h11x2_ck",
0442     "rmii_clk_ck",
0443     NULL,
0444 };
0445
0446 static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
0447     "video1_clkin_ck",
0448     "video2_clkin_ck",
0449     "dpll_abe_m2_ck",
0450     "hdmi_clkin_ck",
0451     "l3_iclk_div",
0452     NULL,
0453 };
0454
0455 static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
0456     { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
0457     { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
0458     { 0 },
0459 };
0460
0461 static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
0462     { DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
0463     { 0 },
0464 };
0465
0466 static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
0467     "timer_sys_clk_div",
0468     "sys_32k_ck",
0469     "sys_clkin2",
0470     "ref_clkin0_ck",
0471     "ref_clkin1_ck",
0472     "ref_clkin2_ck",
0473     "ref_clkin3_ck",
0474     "abe_giclk_div",
0475     "video1_div_clk",
0476     "video2_div_clk",
0477     "hdmi_div_clk",
0478     NULL,
0479 };
0480
0481 static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
0482     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0483     { 0 },
0484 };
0485
0486 static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
0487     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0488     { 0 },
0489 };
0490
0491 static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
0492     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0493     { 0 },
0494 };
0495
0496 static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
0497     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0498     { 0 },
0499 };
0500
0501 static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
0502     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0503     { 0 },
0504 };
0505
0506 static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
0507     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0508     { 0 },
0509 };
0510
0511 static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
0512     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0513     { 0 },
0514 };
0515
0516 static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
0517     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0518     { 0 },
0519 };
0520
0521 static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
0522     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0523     { 0 },
0524 };
0525
0526 static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
0527     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0528     { 0 },
0529 };
0530
0531 static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
0532     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0533     { 0 },
0534 };
0535
0536 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
0537     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0538     { 0 },
0539 };
0540
0541 static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
0542     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0543     { 0 },
0544 };
0545
0546 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
0547     "l4per-clkctrl:00f8:24",
0548     NULL,
0549 };
0550
0551 static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
0552     .max_div = 4,
0553     .flags = CLK_DIVIDER_POWER_OF_TWO,
0554 };
0555
0556 static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
0557     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0558     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0559     { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
0560     { 0 },
0561 };
0562
0563 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
0564     "l4per-clkctrl:0100:24",
0565     NULL,
0566 };
0567
0568 static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
0569     .max_div = 4,
0570     .flags = CLK_DIVIDER_POWER_OF_TWO,
0571 };
0572
0573 static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
0574     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0575     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0576     { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
0577     { 0 },
0578 };
0579
0580 static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
0581     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0582     { 0 },
0583 };
0584
0585 static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
0586     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0587     { 0 },
0588 };
0589
0590 static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
0591     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0592     { 0 },
0593 };
0594
0595 static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
0596     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0597     { 0 },
0598 };
0599
0600 static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
0601     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0602     { 0 },
0603 };
0604
0605 static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
0606     { DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
0607     { DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
0608     { DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
0609     { DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
0610     { DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
0611     { DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
0612     { DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
0613     { DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0614     { DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0615     { DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0616     { DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0617     { DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0618     { DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
0619     { DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0620     { DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0621     { DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0622     { DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0623     { DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
0624     { DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0625     { DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0626     { DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0627     { DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0628     { DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0629     { DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
0630     { DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
0631     { DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
0632     { DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
0633     { DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
0634     { DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
0635     { DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
0636     { DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
0637     { 0 },
0638 };
0639
0640 static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
0641     { DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0642     { DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0643     { DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0644     { DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
0645     { DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0646     { DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0647     { 0 },
0648 };
0649
0650 static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
0651     "func_128m_clk",
0652     "dpll_per_h13x2_ck",
0653     NULL,
0654 };
0655
0656 static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
0657     "l4per2-clkctrl:012c:24",
0658     NULL,
0659 };
0660
0661 static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
0662     .max_div = 4,
0663     .flags = CLK_DIVIDER_POWER_OF_TWO,
0664 };
0665
0666 static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
0667     { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
0668     { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
0669     { 0 },
0670 };
0671
0672 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
0673     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0674     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0675     { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0676     { 0 },
0677 };
0678
0679 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
0680     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0681     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0682     { 0 },
0683 };
0684
0685 static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
0686     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0687     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0688     { 0 },
0689 };
0690
0691 static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
0692     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0693     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0694     { 0 },
0695 };
0696
0697 static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
0698     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0699     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0700     { 0 },
0701 };
0702
0703 static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
0704     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0705     { 0 },
0706 };
0707
0708 static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
0709     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0710     { 0 },
0711 };
0712
0713 static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
0714     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0715     { 0 },
0716 };
0717
0718 static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
0719     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0720     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0721     { 0 },
0722 };
0723
0724 static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
0725     { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
0726     { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
0727     { 0 },
0728 };
0729
0730 static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
0731     { DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
0732     { DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
0733     { DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
0734     { DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
0735     { DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
0736     { DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
0737     { DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
0738     { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
0739     { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
0740     { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
0741     { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
0742     { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
0743     { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
0744     { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
0745     { DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
0746     { DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
0747     { DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
0748     { DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
0749     { 0 },
0750 };
0751
0752 static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
0753     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0754     { 0 },
0755 };
0756
0757 static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
0758     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0759     { 0 },
0760 };
0761
0762 static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
0763     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0764     { 0 },
0765 };
0766
0767 static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
0768     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0769     { 0 },
0770 };
0771
0772 static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
0773     { DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
0774     { DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
0775     { DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
0776     { DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
0777     { DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
0778     { 0 },
0779 };
0780
0781 static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
0782     { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
0783     { 0 },
0784 };
0785
0786 static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
0787     { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
0788     { 0 },
0789 };
0790
0791 static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
0792     { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
0793     { 0 },
0794 };
0795
0796 static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
0797     "sys_clkin1",
0798     "sys_clkin2",
0799     NULL,
0800 };
0801
0802 static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
0803     { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
0804     { 0 },
0805 };
0806
0807 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
0808     { DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
0809     { DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0810     { DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
0811     { DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
0812     { DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
0813     { DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
0814     { DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
0815     { DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
0816     { DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
0817     { 0 },
0818 };
0819
0820 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
0821     { 0x4a005320, dra7_mpu_clkctrl_regs },
0822     { 0x4a005420, dra7_dsp1_clkctrl_regs },
0823     { 0x4a005520, dra7_ipu1_clkctrl_regs },
0824     { 0x4a005550, dra7_ipu_clkctrl_regs },
0825     { 0x4a005620, dra7_dsp2_clkctrl_regs },
0826     { 0x4a005720, dra7_rtc_clkctrl_regs },
0827     { 0x4a005760, dra7_vpe_clkctrl_regs },
0828     { 0x4a008620, dra7_coreaon_clkctrl_regs },
0829     { 0x4a008720, dra7_l3main1_clkctrl_regs },
0830     { 0x4a008920, dra7_ipu2_clkctrl_regs },
0831     { 0x4a008a20, dra7_dma_clkctrl_regs },
0832     { 0x4a008b20, dra7_emif_clkctrl_regs },
0833     { 0x4a008c00, dra7_atl_clkctrl_regs },
0834     { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
0835     { 0x4a008e20, dra7_l3instr_clkctrl_regs },
0836     { 0x4a008f20, dra7_iva_clkctrl_regs },
0837     { 0x4a009020, dra7_cam_clkctrl_regs },
0838     { 0x4a009120, dra7_dss_clkctrl_regs },
0839     { 0x4a009220, dra7_gpu_clkctrl_regs },
0840     { 0x4a009320, dra7_l3init_clkctrl_regs },
0841     { 0x4a0093b0, dra7_pcie_clkctrl_regs },
0842     { 0x4a0093d0, dra7_gmac_clkctrl_regs },
0843     { 0x4a009728, dra7_l4per_clkctrl_regs },
0844     { 0x4a0098a0, dra7_l4sec_clkctrl_regs },
0845     { 0x4a00970c, dra7_l4per2_clkctrl_regs },
0846     { 0x4a009714, dra7_l4per3_clkctrl_regs },
0847     { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
0848     { 0 },
0849 };
0850
0851 static struct ti_dt_clk dra7xx_clks[] = {
0852     DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
0853     DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
0854     DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
0855     DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
0856     DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
0857     DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
0858     DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
0859     DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
0860     DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
0861     DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
0862     DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
0863     DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
0864     DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
0865     DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
0866     DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
0867     DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
0868     DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
0869     DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
0870     DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
0871     DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
0872     DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
0873     DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
0874     DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
0875     DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
0876     DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
0877     DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
0878     DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
0879     DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
0880     DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
0881     DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
0882     DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
0883     DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
0884     DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
0885     DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
0886     DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
0887     DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
0888     DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
0889     DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
0890     DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
0891     DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
0892     DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
0893     DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
0894     DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
0895     DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
0896     DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
0897     DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
0898     DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
0899     DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
0900     DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
0901     DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
0902     DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
0903     DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
0904     DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
0905     DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
0906     DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
0907     DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
0908     DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
0909     DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
0910     DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
0911     DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
0912     DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
0913     DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
0914     DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
0915     DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
0916     DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
0917     DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
0918     DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
0919     DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
0920     DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
0921     DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
0922     DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
0923     DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
0924     DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
0925     DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
0926     DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
0927     DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
0928     DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
0929     DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
0930     DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
0931     DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
0932     DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
0933     DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
0934     DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
0935     DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
0936     DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
0937     DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
0938     DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
0939     DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
0940     DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
0941     { .node_name = NULL },
0942 };
0943
0944 int __init dra7xx_dt_clk_init(void)
0945 {
0946     int rc;
0947     struct clk *dpll_ck, *hdcp_ck;
0948
0949     ti_dt_clocks_register(dra7xx_clks);
0950
0951     omap2_clk_disable_autoidle_all();
0952
0953     ti_clk_add_aliases();
0954
0955     dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
0956     rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
0957     if (rc)
0958         pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
0959
0960     dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
0961     rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
0962     if (rc)
0963         pr_err("%s: failed to configure USB DPLL!\n", __func__);
0964
0965     dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
0966     rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
0967     if (rc)
0968         pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
0969
0970     hdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk");
0971     rc = clk_prepare_enable(hdcp_ck);
0972     if (rc)
0973         pr_err("%s: failed to set dss_deshdcp_clk\n", __func__);
0974
0975     return rc;
0976 }