clk/ti/clk-54xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP5 Clock init
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  *
0007  * Tero Kristo (t-kristo@ti.com)
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/list.h>
0012 #include <linux/clk.h>
0013 #include <linux/clkdev.h>
0014 #include <linux/io.h>
0015 #include <linux/clk/ti.h>
0016 #include <dt-bindings/clock/omap5.h>
0017
0018 #include "clock.h"
0019
0020 #define OMAP5_DPLL_ABE_DEFFREQ              98304000
0021
0022 /*
0023  * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
0024  * states it must be at 960MHz
0025  */
0026 #define OMAP5_DPLL_USB_DEFFREQ              960000000
0027
0028 static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
0029     { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
0030     { 0 },
0031 };
0032
0033 static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
0034     { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
0035     { 0 },
0036 };
0037
0038 static const char * const omap5_aess_fclk_parents[] __initconst = {
0039     "abe_clk",
0040     NULL,
0041 };
0042
0043 static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
0044     .max_div = 2,
0045 };
0046
0047 static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
0048     { 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
0049     { 0 },
0050 };
0051
0052 static const char * const omap5_dmic_gfclk_parents[] __initconst = {
0053     "abe-clkctrl:0018:26",
0054     "pad_clks_ck",
0055     "slimbus_clk",
0056     NULL,
0057 };
0058
0059 static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
0060     "abe_24m_fclk",
0061     "dss_syc_gfclk_div",
0062     "func_24m_clk",
0063     NULL,
0064 };
0065
0066 static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
0067     { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
0068     { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
0069     { 0 },
0070 };
0071
0072 static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
0073     "abe-clkctrl:0028:26",
0074     "pad_clks_ck",
0075     "slimbus_clk",
0076     NULL,
0077 };
0078
0079 static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
0080     { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
0081     { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
0082     { 0 },
0083 };
0084
0085 static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
0086     "abe-clkctrl:0030:26",
0087     "pad_clks_ck",
0088     "slimbus_clk",
0089     NULL,
0090 };
0091
0092 static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
0093     { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
0094     { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
0095     { 0 },
0096 };
0097
0098 static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
0099     "abe-clkctrl:0038:26",
0100     "pad_clks_ck",
0101     "slimbus_clk",
0102     NULL,
0103 };
0104
0105 static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
0106     { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
0107     { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
0108     { 0 },
0109 };
0110
0111 static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
0112     "dss_syc_gfclk_div",
0113     "sys_32k_ck",
0114     NULL,
0115 };
0116
0117 static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
0118     { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
0119     { 0 },
0120 };
0121
0122 static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
0123     { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
0124     { 0 },
0125 };
0126
0127 static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
0128     { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
0129     { 0 },
0130 };
0131
0132 static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
0133     { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
0134     { 0 },
0135 };
0136
0137 static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
0138     { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
0139     { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
0140     { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
0141     { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
0142     { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
0143     { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
0144     { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
0145     { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
0146     { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
0147     { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
0148     { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
0149     { 0 },
0150 };
0151
0152 static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
0153     { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
0154     { 0 },
0155 };
0156
0157 static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
0158     { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
0159     { OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0160     { OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0161     { 0 },
0162 };
0163
0164 static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
0165     { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
0166     { 0 },
0167 };
0168
0169 static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
0170     { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
0171     { 0 },
0172 };
0173
0174 static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
0175     { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
0176     { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
0177     { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
0178     { 0 },
0179 };
0180
0181 static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
0182     { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
0183     { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
0184     { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
0185     { 0 },
0186 };
0187
0188 static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
0189     { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0190     { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0191     { 0 },
0192 };
0193
0194 static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
0195     "sys_clkin",
0196     "sys_32k_ck",
0197     NULL,
0198 };
0199
0200 static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
0201     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0202     { 0 },
0203 };
0204
0205 static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
0206     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0207     { 0 },
0208 };
0209
0210 static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
0211     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0212     { 0 },
0213 };
0214
0215 static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
0216     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0217     { 0 },
0218 };
0219
0220 static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
0221     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0222     { 0 },
0223 };
0224
0225 static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
0226     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0227     { 0 },
0228 };
0229
0230 static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
0231     "sys_32k_ck",
0232     NULL,
0233 };
0234
0235 static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
0236     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0237     { 0 },
0238 };
0239
0240 static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
0241     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0242     { 0 },
0243 };
0244
0245 static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
0246     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0247     { 0 },
0248 };
0249
0250 static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
0251     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0252     { 0 },
0253 };
0254
0255 static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
0256     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0257     { 0 },
0258 };
0259
0260 static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
0261     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0262     { 0 },
0263 };
0264
0265 static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
0266     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0267     { 0 },
0268 };
0269
0270 static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
0271     { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
0272     { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
0273     { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
0274     { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
0275     { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
0276     { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
0277     { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0278     { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0279     { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0280     { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0281     { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0282     { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0283     { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0284     { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0285     { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0286     { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
0287     { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0288     { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0289     { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0290     { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0291     { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0292     { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0293     { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0294     { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0295     { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0296     { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0297     { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0298     { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0299     { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0300     { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0301     { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0302     { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0303     { 0 },
0304 };
0305
0306 static const struct
0307 omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
0308     { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0309     { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0310     { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
0311     { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
0312     { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
0313     { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
0314     { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
0315     { 0 },
0316 };
0317
0318 static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
0319     { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
0320     { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
0321     { 0 },
0322 };
0323
0324 static const char * const omap5_dss_dss_clk_parents[] __initconst = {
0325     "dpll_per_h12x2_ck",
0326     NULL,
0327 };
0328
0329 static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
0330     "func_48m_fclk",
0331     NULL,
0332 };
0333
0334 static const char * const omap5_dss_sys_clk_parents[] __initconst = {
0335     "dss_syc_gfclk_div",
0336     NULL,
0337 };
0338
0339 static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
0340     { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
0341     { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
0342     { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
0343     { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0344     { 0 },
0345 };
0346
0347 static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
0348     { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
0349     { 0 },
0350 };
0351
0352 static const char * const omap5_gpu_core_mux_parents[] __initconst = {
0353     "dpll_core_h14x2_ck",
0354     "dpll_per_h14x2_ck",
0355     NULL,
0356 };
0357
0358 static const char * const omap5_gpu_hyd_mux_parents[] __initconst = {
0359     "dpll_core_h14x2_ck",
0360     "dpll_per_h14x2_ck",
0361     NULL,
0362 };
0363
0364 static const char * const omap5_gpu_sys_clk_parents[] __initconst = {
0365     "sys_clkin",
0366     NULL,
0367 };
0368
0369 static const struct omap_clkctrl_div_data omap5_gpu_sys_clk_data __initconst = {
0370     .max_div = 2,
0371 };
0372
0373 static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst = {
0374     { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
0375     { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
0376     { 26, TI_CLK_DIVIDER, omap5_gpu_sys_clk_parents, &omap5_gpu_sys_clk_data },
0377     { 0 },
0378 };
0379
0380 static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
0381     { OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
0382     { 0 },
0383 };
0384
0385 static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
0386     "func_128m_clk",
0387     "dpll_per_m2x2_ck",
0388     NULL,
0389 };
0390
0391 static const char * const omap5_mmc1_fclk_parents[] __initconst = {
0392     "l3init-clkctrl:0008:24",
0393     NULL,
0394 };
0395
0396 static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
0397     .max_div = 2,
0398 };
0399
0400 static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
0401     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0402     { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
0403     { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
0404     { 0 },
0405 };
0406
0407 static const char * const omap5_mmc2_fclk_parents[] __initconst = {
0408     "l3init-clkctrl:0010:24",
0409     NULL,
0410 };
0411
0412 static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
0413     .max_div = 2,
0414 };
0415
0416 static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
0417     { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
0418     { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
0419     { 0 },
0420 };
0421
0422 static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
0423     "l3init_60m_fclk",
0424     NULL,
0425 };
0426
0427 static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
0428     "dpll_usb_m2_ck",
0429     NULL,
0430 };
0431
0432 static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
0433     "l3init-clkctrl:0038:24",
0434     NULL,
0435 };
0436
0437 static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
0438     "l3init-clkctrl:0038:25",
0439     NULL,
0440 };
0441
0442 static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
0443     "l3init_60m_fclk",
0444     "xclk60mhsp1_ck",
0445     NULL,
0446 };
0447
0448 static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
0449     "l3init_60m_fclk",
0450     "xclk60mhsp2_ck",
0451     NULL,
0452 };
0453
0454 static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
0455     { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0456     { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
0457     { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
0458     { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
0459     { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0460     { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0461     { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0462     { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
0463     { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
0464     { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
0465     { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
0466     { 0 },
0467 };
0468
0469 static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
0470     { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0471     { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0472     { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
0473     { 0 },
0474 };
0475
0476 static const char * const omap5_sata_ref_clk_parents[] __initconst = {
0477     "sys_clkin",
0478     NULL,
0479 };
0480
0481 static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
0482     { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
0483     { 0 },
0484 };
0485
0486 static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
0487     "dpll_usb_clkdcoldo",
0488     NULL,
0489 };
0490
0491 static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
0492     { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
0493     { 0 },
0494 };
0495
0496 static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
0497     { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
0498     { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
0499     { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
0500     { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
0501     { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
0502     { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
0503     { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
0504     { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
0505     { 0 },
0506 };
0507
0508 static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
0509     { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
0510     { 0 },
0511 };
0512
0513 static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
0514     { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
0515     { 0 },
0516 };
0517
0518 static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
0519     { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
0520     { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0521     { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
0522     { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
0523     { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
0524     { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0525     { 0 },
0526 };
0527
0528 const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
0529     { 0x4a004320, omap5_mpu_clkctrl_regs },
0530     { 0x4a004420, omap5_dsp_clkctrl_regs },
0531     { 0x4a004520, omap5_abe_clkctrl_regs },
0532     { 0x4a008720, omap5_l3main1_clkctrl_regs },
0533     { 0x4a008820, omap5_l3main2_clkctrl_regs },
0534     { 0x4a008920, omap5_ipu_clkctrl_regs },
0535     { 0x4a008a20, omap5_dma_clkctrl_regs },
0536     { 0x4a008b20, omap5_emif_clkctrl_regs },
0537     { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
0538     { 0x4a008e20, omap5_l3instr_clkctrl_regs },
0539     { 0x4a009020, omap5_l4per_clkctrl_regs },
0540     { 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
0541     { 0x4a009220, omap5_iva_clkctrl_regs },
0542     { 0x4a009420, omap5_dss_clkctrl_regs },
0543     { 0x4a009520, omap5_gpu_clkctrl_regs },
0544     { 0x4a009620, omap5_l3init_clkctrl_regs },
0545     { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
0546     { 0 },
0547 };
0548
0549 static struct ti_dt_clk omap54xx_clks[] = {
0550     DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
0551     DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
0552     DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
0553     DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
0554     DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
0555     DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
0556     DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
0557     DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
0558     DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
0559     DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
0560     DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
0561     DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
0562     DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
0563     DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
0564     DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
0565     DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
0566     DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
0567     DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
0568     DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
0569     DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
0570     DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
0571     DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
0572     DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
0573     DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
0574     DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
0575     DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
0576     DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
0577     DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
0578     DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
0579     DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
0580     DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
0581     DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
0582     DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
0583     DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
0584     DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
0585     DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
0586     DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
0587     DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
0588     DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
0589     DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
0590     DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
0591     DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
0592     DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
0593     DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
0594     DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
0595     DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
0596     DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
0597     DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
0598     DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
0599     DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
0600     DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
0601     DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
0602     DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
0603     DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
0604     { .node_name = NULL },
0605 };
0606
0607 int __init omap5xxx_dt_clk_init(void)
0608 {
0609     int rc;
0610     struct clk *abe_dpll_ref, *abe_dpll, *abe_dpll_byp, *sys_32k_ck, *usb_dpll;
0611
0612     ti_dt_clocks_register(omap54xx_clks);
0613
0614     omap2_clk_disable_autoidle_all();
0615
0616     ti_clk_add_aliases();
0617
0618     abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
0619     sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
0620     rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
0621
0622     /*
0623      * This must also be set to sys_32k_ck to match or
0624      * the ABE DPLL will not lock on a warm reboot when
0625      * ABE timers are used.
0626      */
0627     abe_dpll_byp = clk_get_sys(NULL, "abe_dpll_bypass_clk_mux");
0628     if (!rc)
0629         rc = clk_set_parent(abe_dpll_byp, sys_32k_ck);
0630
0631     abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
0632     if (!rc)
0633         rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ);
0634     if (rc)
0635         pr_err("%s: failed to configure ABE DPLL!\n", __func__);
0636
0637     abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
0638     if (!rc)
0639         rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);
0640     if (rc)
0641         pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);
0642
0643     usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
0644     rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);
0645     if (rc)
0646         pr_err("%s: failed to configure USB DPLL!\n", __func__);
0647
0648     usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");
0649     rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ/2);
0650     if (rc)
0651         pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
0652
0653     return 0;
0654 }