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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * OMAP4 Clock init
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc.
0006  *
0007  * Tero Kristo (t-kristo@ti.com)
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/list.h>
0012 #include <linux/clk.h>
0013 #include <linux/clkdev.h>
0014 #include <linux/clk/ti.h>
0015 #include <dt-bindings/clock/omap4.h>
0016 
0017 #include "clock.h"
0018 
0019 /*
0020  * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
0021  * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
0022  * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
0023  * half of this value.
0024  */
0025 #define OMAP4_DPLL_ABE_DEFFREQ              98304000
0026 
0027 /*
0028  * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
0029  * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
0030  * locked frequency for the USB DPLL is 960MHz.
0031  */
0032 #define OMAP4_DPLL_USB_DEFFREQ              960000000
0033 
0034 static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
0035     { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
0036     { 0 },
0037 };
0038 
0039 static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
0040     { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" },
0041     { 0 },
0042 };
0043 
0044 static const char * const omap4_aess_fclk_parents[] __initconst = {
0045     "abe_clk",
0046     NULL,
0047 };
0048 
0049 static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
0050     .max_div = 2,
0051 };
0052 
0053 static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
0054     { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
0055     { 0 },
0056 };
0057 
0058 static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
0059     "abe-clkctrl:0018:26",
0060     "pad_clks_ck",
0061     "slimbus_clk",
0062     NULL,
0063 };
0064 
0065 static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
0066     "abe_24m_fclk",
0067     "syc_clk_div_ck",
0068     "func_24m_clk",
0069     NULL,
0070 };
0071 
0072 static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
0073     { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
0074     { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
0075     { 0 },
0076 };
0077 
0078 static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
0079     "abe-clkctrl:0020:26",
0080     "pad_clks_ck",
0081     "slimbus_clk",
0082     NULL,
0083 };
0084 
0085 static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
0086     { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
0087     { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
0088     { 0 },
0089 };
0090 
0091 static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
0092     "abe-clkctrl:0028:26",
0093     "pad_clks_ck",
0094     "slimbus_clk",
0095     NULL,
0096 };
0097 
0098 static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
0099     { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
0100     { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
0101     { 0 },
0102 };
0103 
0104 static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
0105     "abe-clkctrl:0030:26",
0106     "pad_clks_ck",
0107     "slimbus_clk",
0108     NULL,
0109 };
0110 
0111 static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
0112     { 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
0113     { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
0114     { 0 },
0115 };
0116 
0117 static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
0118     "abe-clkctrl:0038:26",
0119     "pad_clks_ck",
0120     "slimbus_clk",
0121     NULL,
0122 };
0123 
0124 static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
0125     { 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
0126     { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
0127     { 0 },
0128 };
0129 
0130 static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
0131     "abe_24m_fclk",
0132     NULL,
0133 };
0134 
0135 static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
0136     "func_24m_clk",
0137     NULL,
0138 };
0139 
0140 static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
0141     "pad_clks_ck",
0142     NULL,
0143 };
0144 
0145 static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
0146     "slimbus_clk",
0147     NULL,
0148 };
0149 
0150 static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
0151     { 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
0152     { 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
0153     { 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
0154     { 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
0155     { 0 },
0156 };
0157 
0158 static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
0159     "syc_clk_div_ck",
0160     "sys_32k_ck",
0161     NULL,
0162 };
0163 
0164 static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
0165     { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
0166     { 0 },
0167 };
0168 
0169 static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
0170     { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
0171     { 0 },
0172 };
0173 
0174 static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
0175     { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
0176     { 0 },
0177 };
0178 
0179 static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
0180     { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
0181     { 0 },
0182 };
0183 
0184 static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
0185     { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
0186     { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
0187     { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
0188     { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
0189     { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
0190     { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
0191     { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
0192     { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
0193     { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
0194     { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
0195     { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
0196     { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
0197     { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
0198     { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0199     { 0 },
0200 };
0201 
0202 static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
0203     { OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
0204     { OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
0205     { OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
0206     { 0 },
0207 };
0208 
0209 static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
0210     { OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
0211     { 0 },
0212 };
0213 
0214 static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
0215     { OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
0216     { OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
0217     { OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
0218     { 0 },
0219 };
0220 
0221 static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
0222     { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" },
0223     { 0 },
0224 };
0225 
0226 static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
0227     { OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
0228     { 0 },
0229 };
0230 
0231 static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
0232     { OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
0233     { OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
0234     { OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
0235     { 0 },
0236 };
0237 
0238 static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
0239     { OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
0240     { 0 },
0241 };
0242 
0243 static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
0244     { OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
0245     { OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
0246     { OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
0247     { 0 },
0248 };
0249 
0250 static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
0251     { OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
0252     { OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
0253     { OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
0254     { 0 },
0255 };
0256 
0257 static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
0258     { OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m5x2_ck" },
0259     { OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
0260     { 0 },
0261 };
0262 
0263 static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
0264     "func_96m_fclk",
0265     NULL,
0266 };
0267 
0268 static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
0269     { 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
0270     { 0 },
0271 };
0272 
0273 static const char * const omap4_fdif_fck_parents[] __initconst = {
0274     "dpll_per_m4x2_ck",
0275     NULL,
0276 };
0277 
0278 static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
0279     .max_div = 4,
0280     .flags = CLK_DIVIDER_POWER_OF_TWO,
0281 };
0282 
0283 static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
0284     { 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
0285     { 0 },
0286 };
0287 
0288 static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
0289     { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
0290     { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
0291     { 0 },
0292 };
0293 
0294 static const char * const omap4_dss_dss_clk_parents[] __initconst = {
0295     "dpll_per_m5x2_ck",
0296     NULL,
0297 };
0298 
0299 static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
0300     "func_48mc_fclk",
0301     NULL,
0302 };
0303 
0304 static const char * const omap4_dss_sys_clk_parents[] __initconst = {
0305     "syc_clk_div_ck",
0306     NULL,
0307 };
0308 
0309 static const char * const omap4_dss_tv_clk_parents[] __initconst = {
0310     "extalt_clkin_ck",
0311     NULL,
0312 };
0313 
0314 static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
0315     { 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
0316     { 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
0317     { 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
0318     { 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
0319     { 0 },
0320 };
0321 
0322 static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
0323     { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
0324     { 0 },
0325 };
0326 
0327 static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
0328     "dpll_core_m7x2_ck",
0329     "dpll_per_m7x2_ck",
0330     NULL,
0331 };
0332 
0333 static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
0334     { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
0335     { 0 },
0336 };
0337 
0338 static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
0339     { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
0340     { 0 },
0341 };
0342 
0343 static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
0344     "func_64m_fclk",
0345     "func_96m_fclk",
0346     NULL,
0347 };
0348 
0349 static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
0350     { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
0351     { 0 },
0352 };
0353 
0354 static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
0355     { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
0356     { 0 },
0357 };
0358 
0359 static const char * const omap4_hsi_fck_parents[] __initconst = {
0360     "dpll_per_m2x2_ck",
0361     NULL,
0362 };
0363 
0364 static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
0365     .max_div = 4,
0366     .flags = CLK_DIVIDER_POWER_OF_TWO,
0367 };
0368 
0369 static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
0370     { 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
0371     { 0 },
0372 };
0373 
0374 static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
0375     "l3-init-clkctrl:0038:24",
0376     NULL,
0377 };
0378 
0379 static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
0380     "l3-init-clkctrl:0038:25",
0381     NULL,
0382 };
0383 
0384 static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
0385     "init_60m_fclk",
0386     NULL,
0387 };
0388 
0389 static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
0390     "dpll_usb_m2_ck",
0391     NULL,
0392 };
0393 
0394 static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
0395     "init_60m_fclk",
0396     "xclk60mhsp1_ck",
0397     NULL,
0398 };
0399 
0400 static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
0401     "init_60m_fclk",
0402     "xclk60mhsp2_ck",
0403     NULL,
0404 };
0405 
0406 static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
0407     { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
0408     { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
0409     { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
0410     { 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
0411     { 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
0412     { 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
0413     { 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
0414     { 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
0415     { 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
0416     { 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
0417     { 0 },
0418 };
0419 
0420 static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
0421     "l3-init-clkctrl:0040:24",
0422     NULL,
0423 };
0424 
0425 static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
0426     "utmi_phy_clkout_ck",
0427     "xclk60motg_ck",
0428     NULL,
0429 };
0430 
0431 static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
0432     { 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
0433     { 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
0434     { 0 },
0435 };
0436 
0437 static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
0438     { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
0439     { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
0440     { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
0441     { 0 },
0442 };
0443 
0444 static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
0445     "func_48m_fclk",
0446     NULL,
0447 };
0448 
0449 static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
0450     { 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
0451     { 0 },
0452 };
0453 
0454 static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
0455     { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
0456     { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
0457     { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
0458     { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
0459     { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
0460     { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
0461     { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
0462     { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
0463     { 0 },
0464 };
0465 
0466 static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
0467     "sys_clkin_ck",
0468     "sys_32k_ck",
0469     NULL,
0470 };
0471 
0472 static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
0473     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0474     { 0 },
0475 };
0476 
0477 static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
0478     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0479     { 0 },
0480 };
0481 
0482 static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
0483     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0484     { 0 },
0485 };
0486 
0487 static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
0488     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0489     { 0 },
0490 };
0491 
0492 static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
0493     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0494     { 0 },
0495 };
0496 
0497 static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
0498     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0499     { 0 },
0500 };
0501 
0502 static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
0503     "sys_32k_ck",
0504     NULL,
0505 };
0506 
0507 static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
0508     { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
0509     { 0 },
0510 };
0511 
0512 static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
0513     { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
0514     { 0 },
0515 };
0516 
0517 static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
0518     { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
0519     { 0 },
0520 };
0521 
0522 static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
0523     { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
0524     { 0 },
0525 };
0526 
0527 static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
0528     { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
0529     { 0 },
0530 };
0531 
0532 static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
0533     "l4-per-clkctrl:00c0:26",
0534     "pad_clks_ck",
0535     NULL,
0536 };
0537 
0538 static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
0539     "func_96m_fclk",
0540     "per_abe_nc_fclk",
0541     NULL,
0542 };
0543 
0544 static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
0545     { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
0546     { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
0547     { 0 },
0548 };
0549 
0550 static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
0551     "func_24mc_fclk",
0552     NULL,
0553 };
0554 
0555 static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
0556     "per_abe_24m_fclk",
0557     NULL,
0558 };
0559 
0560 static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
0561     "pad_slimbus_core_clks_ck",
0562     NULL,
0563 };
0564 
0565 static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
0566     { 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
0567     { 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
0568     { 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
0569     { 0 },
0570 };
0571 
0572 static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
0573     { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
0574     { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
0575     { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
0576     { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
0577     { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
0578     { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
0579     { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
0580     { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
0581     { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
0582     { OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
0583     { OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
0584     { OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
0585     { OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
0586     { OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0587     { OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0588     { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0589     { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
0590     { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
0591     { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
0592     { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0593     { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0594     { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0595     { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0596     { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0597     { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0598     { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
0599     { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0600     { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0601     { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0602     { OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0603     { OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
0604     { 0 },
0605 };
0606 
0607 static const struct
0608 omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = {
0609     { OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
0610     { OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
0611     { OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
0612     { OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
0613     { OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_div_ck" },
0614     { OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
0615     { OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_div_ck" },
0616     { 0 },
0617 };
0618 
0619 static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
0620     { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
0621     { 0 },
0622 };
0623 
0624 static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
0625     { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
0626     { 0 },
0627 };
0628 
0629 static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
0630     { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
0631     { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0632     { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
0633     { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
0634     { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
0635     { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
0636     { 0 },
0637 };
0638 
0639 static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
0640     "sys_clkin_ck",
0641     "dpll_core_m6x2_ck",
0642     "tie_low_clock_ck",
0643     NULL,
0644 };
0645 
0646 static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
0647     "emu-sys-clkctrl:0000:22",
0648     NULL,
0649 };
0650 
0651 static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
0652     0,
0653     1,
0654     2,
0655     0,
0656     4,
0657     -1,
0658 };
0659 
0660 static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
0661     .dividers = omap4_trace_clk_div_div_ck_divs,
0662 };
0663 
0664 static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
0665     "emu-sys-clkctrl:0000:20",
0666     NULL,
0667 };
0668 
0669 static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
0670     .max_div = 64,
0671     .flags = CLK_DIVIDER_POWER_OF_TWO,
0672 };
0673 
0674 static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
0675     { 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
0676     { 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
0677     { 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
0678     { 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
0679     { 0 },
0680 };
0681 
0682 static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
0683     { OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
0684     { 0 },
0685 };
0686 
0687 const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
0688     { 0x4a004320, omap4_mpuss_clkctrl_regs },
0689     { 0x4a004420, omap4_tesla_clkctrl_regs },
0690     { 0x4a004520, omap4_abe_clkctrl_regs },
0691     { 0x4a008620, omap4_l4_ao_clkctrl_regs },
0692     { 0x4a008720, omap4_l3_1_clkctrl_regs },
0693     { 0x4a008820, omap4_l3_2_clkctrl_regs },
0694     { 0x4a008920, omap4_ducati_clkctrl_regs },
0695     { 0x4a008a20, omap4_l3_dma_clkctrl_regs },
0696     { 0x4a008b20, omap4_l3_emif_clkctrl_regs },
0697     { 0x4a008c20, omap4_d2d_clkctrl_regs },
0698     { 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
0699     { 0x4a008e20, omap4_l3_instr_clkctrl_regs },
0700     { 0x4a008f20, omap4_ivahd_clkctrl_regs },
0701     { 0x4a009020, omap4_iss_clkctrl_regs },
0702     { 0x4a009120, omap4_l3_dss_clkctrl_regs },
0703     { 0x4a009220, omap4_l3_gfx_clkctrl_regs },
0704     { 0x4a009320, omap4_l3_init_clkctrl_regs },
0705     { 0x4a009420, omap4_l4_per_clkctrl_regs },
0706     { 0x4a0095a0, omap4_l4_secure_clkctrl_regs },
0707     { 0x4a307820, omap4_l4_wkup_clkctrl_regs },
0708     { 0x4a307a20, omap4_emu_sys_clkctrl_regs },
0709     { 0 },
0710 };
0711 
0712 static struct ti_dt_clk omap44xx_clks[] = {
0713     DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
0714     /*
0715      * XXX: All the clock aliases below are only needed for legacy
0716      * hwmod support. Once hwmod is removed, these can be removed
0717      * also.
0718      */
0719     DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
0720     DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
0721     DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
0722     DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
0723     DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
0724     DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
0725     DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
0726     DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
0727     DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
0728     DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
0729     DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
0730     DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
0731     DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
0732     DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
0733     DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
0734     DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
0735     DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
0736     DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
0737     DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
0738     DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
0739     DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
0740     DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
0741     DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
0742     DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
0743     DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
0744     DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
0745     DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
0746     DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
0747     DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
0748     DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
0749     DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
0750     DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
0751     DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
0752     DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
0753     DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
0754     DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
0755     DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
0756     DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
0757     DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
0758     DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
0759     DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
0760     DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
0761     DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
0762     DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
0763     DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
0764     DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
0765     DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
0766     DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
0767     DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
0768     DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
0769     DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
0770     DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
0771     DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
0772     DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
0773     DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
0774     DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
0775     DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
0776     DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
0777     DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
0778     DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
0779     DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
0780     DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
0781     DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
0782     DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
0783     DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
0784     DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
0785     DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
0786     { .node_name = NULL },
0787 };
0788 
0789 int __init omap4xxx_dt_clk_init(void)
0790 {
0791     int rc;
0792     struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
0793 
0794     ti_dt_clocks_register(omap44xx_clks);
0795 
0796     omap2_clk_disable_autoidle_all();
0797 
0798     ti_clk_add_aliases();
0799 
0800     /*
0801      * Lock USB DPLL on OMAP4 devices so that the L3INIT power
0802      * domain can transition to retention state when not in use.
0803      */
0804     usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
0805     rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
0806     if (rc)
0807         pr_err("%s: failed to configure USB DPLL!\n", __func__);
0808 
0809     /*
0810      * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
0811      * state when turning the ABE clock domain. Workaround this by
0812      * locking the ABE DPLL on boot.
0813      * Lock the ABE DPLL in any case to avoid issues with audio.
0814      */
0815     abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
0816     sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
0817     rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
0818     abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
0819     if (!rc)
0820         rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
0821     if (rc)
0822         pr_err("%s: failed to configure ABE DPLL!\n", __func__);
0823 
0824     return 0;
0825 }
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