clk/ti/clk-43xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AM43XX Clock init
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc
0006  *     Tero Kristo (t-kristo@ti.com)
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/list.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/clk/ti.h>
0014 #include <dt-bindings/clock/am4.h>
0015
0016 #include "clock.h"
0017
0018 static const struct omap_clkctrl_reg_data am4_l3s_tsc_clkctrl_regs[] __initconst = {
0019     { AM4_L3S_TSC_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
0020     { 0 },
0021 };
0022
0023 static const char * const am4_synctimer_32kclk_parents[] __initconst = {
0024     "mux_synctimer32k_ck",
0025     NULL,
0026 };
0027
0028 static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
0029     { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
0030     { 0 },
0031 };
0032
0033 static const struct omap_clkctrl_reg_data am4_l4_wkup_aon_clkctrl_regs[] __initconst = {
0034     { AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sys_clkin_ck" },
0035     { AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl:0008:8" },
0036     { 0 },
0037 };
0038
0039 static const char * const am4_gpio0_dbclk_parents[] __initconst = {
0040     "gpio0_dbclk_mux_ck",
0041     NULL,
0042 };
0043
0044 static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
0045     { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
0046     { 0 },
0047 };
0048
0049 static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
0050     { AM4_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
0051     { AM4_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
0052     { AM4_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
0053     { AM4_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
0054     { AM4_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
0055     { AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
0056     { AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
0057     { AM4_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
0058     { AM4_L4_WKUP_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck" },
0059     { 0 },
0060 };
0061
0062 static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
0063     { AM4_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
0064     { 0 },
0065 };
0066
0067 static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
0068     { AM4_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
0069     { 0 },
0070 };
0071
0072 static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
0073     { AM4_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ick" },
0074     { 0 },
0075 };
0076
0077 static const struct omap_clkctrl_reg_data am4_l3_clkctrl_regs[] __initconst = {
0078     { AM4_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0079     { AM4_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
0080     { AM4_L3_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0081     { AM4_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0082     { AM4_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0083     { AM4_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0084     { AM4_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0085     { AM4_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0086     { AM4_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0087     { AM4_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0088     { AM4_L3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
0089     { 0 },
0090 };
0091
0092 static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
0093     "dpll_per_clkdcoldo",
0094     NULL,
0095 };
0096
0097 static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
0098     { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
0099     { 0 },
0100 };
0101
0102 static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
0103     { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
0104     { 0 },
0105 };
0106
0107 static const struct omap_clkctrl_reg_data am4_l3s_clkctrl_regs[] __initconst = {
0108     { AM4_L3S_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0109     { AM4_L3S_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0110     { AM4_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
0111     { AM4_L3S_ADC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
0112     { AM4_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
0113     { AM4_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
0114     { AM4_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
0115     { AM4_L3S_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
0116     { AM4_L3S_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk" },
0117     { AM4_L3S_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk" },
0118     { 0 },
0119 };
0120
0121 static const struct omap_clkctrl_reg_data am4_pruss_ocp_clkctrl_regs[] __initconst = {
0122     { AM4_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
0123     { 0 },
0124 };
0125
0126 static const char * const am4_gpio1_dbclk_parents[] __initconst = {
0127     "clkdiv32k_ick",
0128     NULL,
0129 };
0130
0131 static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
0132     { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
0133     { 0 },
0134 };
0135
0136 static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
0137     { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
0138     { 0 },
0139 };
0140
0141 static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
0142     { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
0143     { 0 },
0144 };
0145
0146 static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
0147     { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
0148     { 0 },
0149 };
0150
0151 static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
0152     { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
0153     { 0 },
0154 };
0155
0156 static const struct omap_clkctrl_reg_data am4_l4ls_clkctrl_regs[] __initconst = {
0157     { AM4_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0158     { AM4_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
0159     { AM4_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
0160     { AM4_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0161     { AM4_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0162     { AM4_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0163     { AM4_L4LS_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0164     { AM4_L4LS_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0165     { AM4_L4LS_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0166     { AM4_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0167     { AM4_L4LS_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0168     { AM4_L4LS_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0169     { AM4_L4LS_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0170     { AM4_L4LS_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0171     { AM4_L4LS_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0172     { AM4_L4LS_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
0173     { AM4_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0174     { AM4_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0175     { AM4_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0176     { AM4_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
0177     { AM4_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
0178     { AM4_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
0179     { AM4_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0180     { AM4_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0181     { AM4_L4LS_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0182     { AM4_L4LS_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0183     { AM4_L4LS_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0184     { AM4_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0185     { AM4_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
0186     { AM4_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
0187     { AM4_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
0188     { AM4_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
0189     { AM4_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
0190     { AM4_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
0191     { AM4_L4LS_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
0192     { AM4_L4LS_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
0193     { AM4_L4LS_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
0194     { AM4_L4LS_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
0195     { AM4_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0196     { AM4_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0197     { AM4_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0198     { AM4_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0199     { AM4_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0200     { AM4_L4LS_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0201     { AM4_L4LS_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0202     { 0 },
0203 };
0204
0205 static const struct omap_clkctrl_reg_data am4_emif_clkctrl_regs[] __initconst = {
0206     { AM4_EMIF_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck" },
0207     { 0 },
0208 };
0209
0210 static const struct omap_clkctrl_reg_data am4_dss_clkctrl_regs[] __initconst = {
0211     { AM4_DSS_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "disp_clk" },
0212     { 0 },
0213 };
0214
0215 static const struct omap_clkctrl_reg_data am4_cpsw_125mhz_clkctrl_regs[] __initconst = {
0216     { AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
0217     { 0 },
0218 };
0219
0220 const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
0221     { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
0222     { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
0223     { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
0224     { 0x44df8320, am4_mpu_clkctrl_regs },
0225     { 0x44df8420, am4_gfx_l3_clkctrl_regs },
0226     { 0x44df8520, am4_l4_rtc_clkctrl_regs },
0227     { 0x44df8820, am4_l3_clkctrl_regs },
0228     { 0x44df8868, am4_l3s_clkctrl_regs },
0229     { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
0230     { 0x44df8c20, am4_l4ls_clkctrl_regs },
0231     { 0x44df8f20, am4_emif_clkctrl_regs },
0232     { 0x44df9220, am4_dss_clkctrl_regs },
0233     { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
0234     { 0 },
0235 };
0236
0237 const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
0238     { 0x44df2920, am4_l3s_tsc_clkctrl_regs },
0239     { 0x44df2a28, am4_l4_wkup_aon_clkctrl_regs },
0240     { 0x44df2a20, am4_l4_wkup_clkctrl_regs },
0241     { 0x44df8320, am4_mpu_clkctrl_regs },
0242     { 0x44df8420, am4_gfx_l3_clkctrl_regs },
0243     { 0x44df8820, am4_l3_clkctrl_regs },
0244     { 0x44df8868, am4_l3s_clkctrl_regs },
0245     { 0x44df8b20, am4_pruss_ocp_clkctrl_regs },
0246     { 0x44df8c20, am4_l4ls_clkctrl_regs },
0247     { 0x44df8f20, am4_emif_clkctrl_regs },
0248     { 0x44df9220, am4_dss_clkctrl_regs },
0249     { 0x44df9320, am4_cpsw_125mhz_clkctrl_regs },
0250     { 0 },
0251 };
0252
0253 static struct ti_dt_clk am43xx_clks[] = {
0254     DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
0255     DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
0256     DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
0257     DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
0258     DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
0259     DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
0260     DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
0261     DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
0262     DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
0263     DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
0264     DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
0265     { .node_name = NULL },
0266 };
0267
0268 static const char *enable_init_clks[] = {
0269     /* AM4_L3_L3_MAIN_CLKCTRL, needed during suspend */
0270     "l3-clkctrl:0000:0",
0271 };
0272
0273 int __init am43xx_dt_clk_init(void)
0274 {
0275     struct clk *clk1, *clk2;
0276
0277     ti_dt_clocks_register(am43xx_clks);
0278
0279     omap2_clk_disable_autoidle_all();
0280
0281     omap2_clk_enable_init_clocks(enable_init_clks,
0282                      ARRAY_SIZE(enable_init_clks));
0283
0284     ti_clk_add_aliases();
0285
0286     /*
0287      * cpsw_cpts_rft_clk  has got the choice of 3 clocksources
0288      * dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
0289      * By default dpll_core_m4_ck is selected, witn this as clock
0290      * source the CPTS doesnot work properly. It gives clockcheck errors
0291      * while running PTP.
0292      * clockcheck: clock jumped backward or running slower than expected!
0293      * By selecting dpll_core_m5_ck as the clocksource fixes this issue.
0294      * In AM335x dpll_core_m5_ck is the default clocksource.
0295      */
0296     clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
0297     clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
0298     clk_set_parent(clk1, clk2);
0299
0300     return 0;
0301 }