clk/ti/clk-33xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * AM33XX Clock init
0004  *
0005  * Copyright (C) 2013 Texas Instruments, Inc
0006  *     Tero Kristo (t-kristo@ti.com)
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/list.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/clk/ti.h>
0014 #include <dt-bindings/clock/am3.h>
0015
0016 #include "clock.h"
0017
0018 static const char * const am3_gpio1_dbclk_parents[] __initconst = {
0019     "clk-24mhz-clkctrl:0000:0",
0020     NULL,
0021 };
0022
0023 static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
0024     { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
0025     { 0 },
0026 };
0027
0028 static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
0029     { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
0030     { 0 },
0031 };
0032
0033 static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
0034     { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
0035     { 0 },
0036 };
0037
0038 static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
0039     { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0040     { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
0041     { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0042     { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0043     { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0044     { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0045     { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0046     { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0047     { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0048     { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0049     { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0050     { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
0051     { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
0052     { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
0053     { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
0054     { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
0055     { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
0056     { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0057     { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0058     { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
0059     { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
0060     { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
0061     { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0062     { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0063     { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0064     { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
0065     { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
0066     { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
0067     { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0068     { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0069     { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
0070     { 0 },
0071 };
0072
0073 static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
0074     { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
0075     { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
0076     { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
0077     { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
0078     { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
0079     { 0 },
0080 };
0081
0082 static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
0083     { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0084     { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
0085     { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0086     { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
0087     { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0088     { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0089     { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0090     { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0091     { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0092     { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
0093     { 0 },
0094 };
0095
0096 static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
0097     { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
0098     { 0 },
0099 };
0100
0101 static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
0102     { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
0103     { 0 },
0104 };
0105
0106 static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
0107     { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
0108     { 0 },
0109 };
0110
0111 static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
0112     { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
0113     { 0 },
0114 };
0115
0116 static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
0117     { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
0118     { 0 },
0119 };
0120
0121 static const char * const am3_gpio0_dbclk_parents[] __initconst = {
0122     "gpio0_dbclk_mux_ck",
0123     NULL,
0124 };
0125
0126 static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
0127     { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
0128     { 0 },
0129 };
0130
0131 static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
0132     { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
0133     { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
0134     { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
0135     { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
0136     { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
0137     { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
0138     { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
0139     { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
0140     { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
0141     { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
0142     { 0 },
0143 };
0144
0145 static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
0146     "sys_clkin_ck",
0147     NULL,
0148 };
0149
0150 static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
0151     "l3-aon-clkctrl:0000:19",
0152     "l3-aon-clkctrl:0000:30",
0153     NULL,
0154 };
0155
0156 static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
0157     "l3-aon-clkctrl:0000:20",
0158     NULL,
0159 };
0160
0161 static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
0162     .max_div = 64,
0163     .flags = CLK_DIVIDER_POWER_OF_TWO,
0164 };
0165
0166 static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
0167     "l3-aon-clkctrl:0000:22",
0168     NULL,
0169 };
0170
0171 static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
0172     .max_div = 64,
0173     .flags = CLK_DIVIDER_POWER_OF_TWO,
0174 };
0175
0176 static const char * const am3_dbg_clka_ck_parents[] __initconst = {
0177     "dpll_core_m4_ck",
0178     NULL,
0179 };
0180
0181 static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
0182     { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
0183     { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
0184     { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
0185     { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
0186     { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
0187     { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
0188     { 0 },
0189 };
0190
0191 static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
0192     { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
0193     { 0 },
0194 };
0195
0196 static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
0197     { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
0198     { 0 },
0199 };
0200
0201 static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
0202     { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
0203     { 0 },
0204 };
0205
0206 static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
0207     { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
0208     { 0 },
0209 };
0210
0211 static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
0212     { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
0213     { 0 },
0214 };
0215
0216 static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
0217     { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
0218     { 0 },
0219 };
0220
0221 const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
0222     { 0x44e00038, am3_l4ls_clkctrl_regs },
0223     { 0x44e0001c, am3_l3s_clkctrl_regs },
0224     { 0x44e00024, am3_l3_clkctrl_regs },
0225     { 0x44e00120, am3_l4hs_clkctrl_regs },
0226     { 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
0227     { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
0228     { 0x44e00018, am3_lcdc_clkctrl_regs },
0229     { 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
0230     { 0x44e00400, am3_l4_wkup_clkctrl_regs },
0231     { 0x44e00414, am3_l3_aon_clkctrl_regs },
0232     { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
0233     { 0x44e00600, am3_mpu_clkctrl_regs },
0234     { 0x44e00800, am3_l4_rtc_clkctrl_regs },
0235     { 0x44e00900, am3_gfx_l3_clkctrl_regs },
0236     { 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
0237     { 0 },
0238 };
0239
0240 static struct ti_dt_clk am33xx_clks[] = {
0241     DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
0242     DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
0243     DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
0244     DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
0245     DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
0246     DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
0247     DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
0248     DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
0249     DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
0250     DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
0251     DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
0252     DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
0253     DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
0254     { .node_name = NULL },
0255 };
0256
0257 static const char *enable_init_clks[] = {
0258     "dpll_ddr_m2_ck",
0259     "dpll_mpu_m2_ck",
0260     "l3_gclk",
0261     /* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */
0262     "l3-clkctrl:00bc:0",
0263     "l4hs_gclk",
0264     "l4fw_gclk",
0265     "l4ls_gclk",
0266     /* Required for external peripherals like, Audio codecs */
0267     "clkout2_ck",
0268 };
0269
0270 int __init am33xx_dt_clk_init(void)
0271 {
0272     struct clk *clk1, *clk2;
0273
0274     ti_dt_clocks_register(am33xx_clks);
0275
0276     omap2_clk_disable_autoidle_all();
0277
0278     ti_clk_add_aliases();
0279
0280     omap2_clk_enable_init_clocks(enable_init_clks,
0281                      ARRAY_SIZE(enable_init_clks));
0282
0283     /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
0284      *    physically present, in such a case HWMOD enabling of
0285      *    clock would be failure with default parent. And timer
0286      *    probe thinks clock is already enabled, this leads to
0287      *    crash upon accessing timer 3 & 6 registers in probe.
0288      *    Fix by setting parent of both these timers to master
0289      *    oscillator clock.
0290      */
0291
0292     clk1 = clk_get_sys(NULL, "sys_clkin_ck");
0293     clk2 = clk_get_sys(NULL, "timer3_fck");
0294     clk_set_parent(clk2, clk1);
0295
0296     clk2 = clk_get_sys(NULL, "timer6_fck");
0297     clk_set_parent(clk2, clk1);
0298     /*
0299      * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
0300      * the design/spec, so as a result, for example, timer which supposed
0301      * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
0302      * not expected by any use-case, so change WDT1 clock source to PRCM
0303      * 32KHz clock.
0304      */
0305     clk1 = clk_get_sys(NULL, "wdt1_fck");
0306     clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
0307     clk_set_parent(clk1, clk2);
0308
0309     return 0;
0310 }