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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 
0003 #include <linux/clk.h>
0004 #include <linux/clkdev.h>
0005 #include <linux/clk-provider.h>
0006 #include <linux/delay.h>
0007 #include <linux/err.h>
0008 #include <linux/io.h>
0009 #include <linux/math64.h>
0010 #include <linux/module.h>
0011 #include <linux/of_device.h>
0012 #include <linux/string.h>
0013 
0014 #define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00    /* Managed by MPPULL */
0015 #define ADPLL_PLLSS_MMR_LOCK_ENABLED    0x1f125B64
0016 #define ADPLL_PLLSS_MMR_UNLOCK_MAGIC    0x1eda4c3d
0017 
0018 #define ADPLL_PWRCTRL_OFFSET        0x00
0019 #define ADPLL_PWRCTRL_PONIN     5
0020 #define ADPLL_PWRCTRL_PGOODIN       4
0021 #define ADPLL_PWRCTRL_RET       3
0022 #define ADPLL_PWRCTRL_ISORET        2
0023 #define ADPLL_PWRCTRL_ISOSCAN       1
0024 #define ADPLL_PWRCTRL_OFFMODE       0
0025 
0026 #define ADPLL_CLKCTRL_OFFSET        0x04
0027 #define ADPLL_CLKCTRL_CLKDCOLDOEN   29
0028 #define ADPLL_CLKCTRL_IDLE      23
0029 #define ADPLL_CLKCTRL_CLKOUTEN      20
0030 #define ADPLL_CLKINPHIFSEL_ADPLL_S  19  /* REVISIT: which bit? */
0031 #define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
0032 #define ADPLL_CLKCTRL_ULOWCLKEN     18
0033 #define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ    17
0034 #define ADPLL_CLKCTRL_M2PWDNZ       16
0035 #define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S   15
0036 #define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
0037 #define ADPLL_CLKCTRL_LPMODE_ADPLL_S    12
0038 #define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S  10
0039 #define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
0040 #define ADPLL_CLKCTRL_TINITZ        0
0041 
0042 #define ADPLL_TENABLE_OFFSET        0x08
0043 #define ADPLL_TENABLEDIV_OFFSET     0x8c
0044 
0045 #define ADPLL_M2NDIV_OFFSET     0x10
0046 #define ADPLL_M2NDIV_M2         16
0047 #define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH   5
0048 #define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH  7
0049 
0050 #define ADPLL_MN2DIV_OFFSET     0x14
0051 #define ADPLL_MN2DIV_N2         16
0052 
0053 #define ADPLL_FRACDIV_OFFSET        0x18
0054 #define ADPLL_FRACDIV_REGSD     24
0055 #define ADPLL_FRACDIV_FRACTIONALM   0
0056 #define ADPLL_FRACDIV_FRACTIONALM_MASK  0x3ffff
0057 
0058 #define ADPLL_BWCTRL_OFFSET     0x1c
0059 #define ADPLL_BWCTRL_BWCONTROL      1
0060 #define ADPLL_BWCTRL_BW_INCR_DECRZ  0
0061 
0062 #define ADPLL_RESERVED_OFFSET       0x20
0063 
0064 #define ADPLL_STATUS_OFFSET     0x24
0065 #define ADPLL_STATUS_PONOUT     31
0066 #define ADPLL_STATUS_PGOODOUT       30
0067 #define ADPLL_STATUS_LDOPWDN        29
0068 #define ADPLL_STATUS_RECAL_BSTATUS3 28
0069 #define ADPLL_STATUS_RECAL_OPPIN    27
0070 #define ADPLL_STATUS_PHASELOCK      10
0071 #define ADPLL_STATUS_FREQLOCK       9
0072 #define ADPLL_STATUS_BYPASSACK      8
0073 #define ADPLL_STATUS_LOSSREF        6
0074 #define ADPLL_STATUS_CLKOUTENACK    5
0075 #define ADPLL_STATUS_LOCK2      4
0076 #define ADPLL_STATUS_M2CHANGEACK    3
0077 #define ADPLL_STATUS_HIGHJITTER     1
0078 #define ADPLL_STATUS_BYPASS     0
0079 #define ADPLL_STATUS_PREPARED_MASK  (BIT(ADPLL_STATUS_PHASELOCK) | \
0080                      BIT(ADPLL_STATUS_FREQLOCK))
0081 
0082 #define ADPLL_M3DIV_OFFSET      0x28    /* Only on MPUPLL */
0083 #define ADPLL_M3DIV_M3          0
0084 #define ADPLL_M3DIV_M3_WIDTH        5
0085 #define ADPLL_M3DIV_M3_MASK     0x1f
0086 
0087 #define ADPLL_RAMPCTRL_OFFSET       0x2c    /* Only on MPUPLL */
0088 #define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
0089 #define ADPLL_RAMPCTRL_CLKRAMPRATE  16
0090 #define ADPLL_RAMPCTRL_RELOCK_RAMP_EN   0
0091 
0092 #define MAX_ADPLL_INPUTS        3
0093 #define MAX_ADPLL_OUTPUTS       4
0094 #define ADPLL_MAX_RETRIES       5
0095 
0096 #define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
0097 #define to_adpll(_hw)   container_of(_hw, struct ti_adpll_data, dco)
0098 #define to_clkout(_hw)  container_of(_hw, struct ti_adpll_clkout_data, hw)
0099 
0100 enum ti_adpll_clocks {
0101     TI_ADPLL_DCO,
0102     TI_ADPLL_DCO_GATE,
0103     TI_ADPLL_N2,
0104     TI_ADPLL_M2,
0105     TI_ADPLL_M2_GATE,
0106     TI_ADPLL_BYPASS,
0107     TI_ADPLL_HIF,
0108     TI_ADPLL_DIV2,
0109     TI_ADPLL_CLKOUT,
0110     TI_ADPLL_CLKOUT2,
0111     TI_ADPLL_M3,
0112 };
0113 
0114 #define TI_ADPLL_NR_CLOCKS  (TI_ADPLL_M3 + 1)
0115 
0116 enum ti_adpll_inputs {
0117     TI_ADPLL_CLKINP,
0118     TI_ADPLL_CLKINPULOW,
0119     TI_ADPLL_CLKINPHIF,
0120 };
0121 
0122 enum ti_adpll_s_outputs {
0123     TI_ADPLL_S_DCOCLKLDO,
0124     TI_ADPLL_S_CLKOUT,
0125     TI_ADPLL_S_CLKOUTX2,
0126     TI_ADPLL_S_CLKOUTHIF,
0127 };
0128 
0129 enum ti_adpll_lj_outputs {
0130     TI_ADPLL_LJ_CLKDCOLDO,
0131     TI_ADPLL_LJ_CLKOUT,
0132     TI_ADPLL_LJ_CLKOUTLDO,
0133 };
0134 
0135 struct ti_adpll_platform_data {
0136     const bool is_type_s;
0137     const int nr_max_inputs;
0138     const int nr_max_outputs;
0139     const int output_index;
0140 };
0141 
0142 struct ti_adpll_clock {
0143     struct clk *clk;
0144     struct clk_lookup *cl;
0145     void (*unregister)(struct clk *clk);
0146 };
0147 
0148 struct ti_adpll_dco_data {
0149     struct clk_hw hw;
0150 };
0151 
0152 struct ti_adpll_clkout_data {
0153     struct ti_adpll_data *adpll;
0154     struct clk_gate gate;
0155     struct clk_hw hw;
0156 };
0157 
0158 struct ti_adpll_data {
0159     struct device *dev;
0160     const struct ti_adpll_platform_data *c;
0161     struct device_node *np;
0162     unsigned long pa;
0163     void __iomem *iobase;
0164     void __iomem *regs;
0165     spinlock_t lock;    /* For ADPLL shared register access */
0166     const char *parent_names[MAX_ADPLL_INPUTS];
0167     struct clk *parent_clocks[MAX_ADPLL_INPUTS];
0168     struct ti_adpll_clock *clocks;
0169     struct clk_onecell_data outputs;
0170     struct ti_adpll_dco_data dco;
0171 };
0172 
0173 static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
0174                      int output_index,
0175                      const char *postfix)
0176 {
0177     const char *name;
0178     int err;
0179 
0180     if (output_index >= 0) {
0181         err = of_property_read_string_index(d->np,
0182                             "clock-output-names",
0183                             output_index,
0184                             &name);
0185         if (err)
0186             return NULL;
0187     } else {
0188         name = devm_kasprintf(d->dev, GFP_KERNEL, "%08lx.adpll.%s",
0189                       d->pa, postfix);
0190     }
0191 
0192     return name;
0193 }
0194 
0195 #define ADPLL_MAX_CON_ID    16  /* See MAX_CON_ID */
0196 
0197 static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
0198                 int index, int output_index, const char *name,
0199                 void (*unregister)(struct clk *clk))
0200 {
0201     struct clk_lookup *cl;
0202     const char *postfix = NULL;
0203     char con_id[ADPLL_MAX_CON_ID];
0204 
0205     d->clocks[index].clk = clock;
0206     d->clocks[index].unregister = unregister;
0207 
0208     /* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
0209     postfix = strrchr(name, '.');
0210     if (postfix && strlen(postfix) > 1) {
0211         if (strlen(postfix) > ADPLL_MAX_CON_ID)
0212             dev_warn(d->dev, "clock %s con_id lookup may fail\n",
0213                  name);
0214         snprintf(con_id, 16, "pll%03lx%s", d->pa & 0xfff, postfix + 1);
0215         cl = clkdev_create(clock, con_id, NULL);
0216         if (!cl)
0217             return -ENOMEM;
0218         d->clocks[index].cl = cl;
0219     } else {
0220         dev_warn(d->dev, "no con_id for clock %s\n", name);
0221     }
0222 
0223     if (output_index < 0)
0224         return 0;
0225 
0226     d->outputs.clks[output_index] = clock;
0227     d->outputs.clk_num++;
0228 
0229     return 0;
0230 }
0231 
0232 static int ti_adpll_init_divider(struct ti_adpll_data *d,
0233                  enum ti_adpll_clocks index,
0234                  int output_index, char *name,
0235                  struct clk *parent_clock,
0236                  void __iomem *reg,
0237                  u8 shift, u8 width,
0238                  u8 clk_divider_flags)
0239 {
0240     const char *child_name;
0241     const char *parent_name;
0242     struct clk *clock;
0243 
0244     child_name = ti_adpll_clk_get_name(d, output_index, name);
0245     if (!child_name)
0246         return -EINVAL;
0247 
0248     parent_name = __clk_get_name(parent_clock);
0249     clock = clk_register_divider(d->dev, child_name, parent_name, 0,
0250                      reg, shift, width, clk_divider_flags,
0251                      &d->lock);
0252     if (IS_ERR(clock)) {
0253         dev_err(d->dev, "failed to register divider %s: %li\n",
0254             name, PTR_ERR(clock));
0255         return PTR_ERR(clock);
0256     }
0257 
0258     return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
0259                     clk_unregister_divider);
0260 }
0261 
0262 static int ti_adpll_init_mux(struct ti_adpll_data *d,
0263                  enum ti_adpll_clocks index,
0264                  char *name, struct clk *clk0,
0265                  struct clk *clk1,
0266                  void __iomem *reg,
0267                  u8 shift)
0268 {
0269     const char *child_name;
0270     const char *parents[2];
0271     struct clk *clock;
0272 
0273     child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
0274     if (!child_name)
0275         return -ENOMEM;
0276     parents[0] = __clk_get_name(clk0);
0277     parents[1] = __clk_get_name(clk1);
0278     clock = clk_register_mux(d->dev, child_name, parents, 2, 0,
0279                  reg, shift, 1, 0, &d->lock);
0280     if (IS_ERR(clock)) {
0281         dev_err(d->dev, "failed to register mux %s: %li\n",
0282             name, PTR_ERR(clock));
0283         return PTR_ERR(clock);
0284     }
0285 
0286     return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
0287                     clk_unregister_mux);
0288 }
0289 
0290 static int ti_adpll_init_gate(struct ti_adpll_data *d,
0291                   enum ti_adpll_clocks index,
0292                   int output_index, char *name,
0293                   struct clk *parent_clock,
0294                   void __iomem *reg,
0295                   u8 bit_idx,
0296                   u8 clk_gate_flags)
0297 {
0298     const char *child_name;
0299     const char *parent_name;
0300     struct clk *clock;
0301 
0302     child_name = ti_adpll_clk_get_name(d, output_index, name);
0303     if (!child_name)
0304         return -EINVAL;
0305 
0306     parent_name = __clk_get_name(parent_clock);
0307     clock = clk_register_gate(d->dev, child_name, parent_name, 0,
0308                   reg, bit_idx, clk_gate_flags,
0309                   &d->lock);
0310     if (IS_ERR(clock)) {
0311         dev_err(d->dev, "failed to register gate %s: %li\n",
0312             name, PTR_ERR(clock));
0313         return PTR_ERR(clock);
0314     }
0315 
0316     return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
0317                     clk_unregister_gate);
0318 }
0319 
0320 static int ti_adpll_init_fixed_factor(struct ti_adpll_data *d,
0321                       enum ti_adpll_clocks index,
0322                       char *name,
0323                       struct clk *parent_clock,
0324                       unsigned int mult,
0325                       unsigned int div)
0326 {
0327     const char *child_name;
0328     const char *parent_name;
0329     struct clk *clock;
0330 
0331     child_name = ti_adpll_clk_get_name(d, -ENODEV, name);
0332     if (!child_name)
0333         return -ENOMEM;
0334 
0335     parent_name = __clk_get_name(parent_clock);
0336     clock = clk_register_fixed_factor(d->dev, child_name, parent_name,
0337                       0, mult, div);
0338     if (IS_ERR(clock))
0339         return PTR_ERR(clock);
0340 
0341     return ti_adpll_setup_clock(d, clock, index, -ENODEV, child_name,
0342                     clk_unregister);
0343 }
0344 
0345 static void ti_adpll_set_idle_bypass(struct ti_adpll_data *d)
0346 {
0347     unsigned long flags;
0348     u32 v;
0349 
0350     spin_lock_irqsave(&d->lock, flags);
0351     v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
0352     v |= BIT(ADPLL_CLKCTRL_IDLE);
0353     writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
0354     spin_unlock_irqrestore(&d->lock, flags);
0355 }
0356 
0357 static void ti_adpll_clear_idle_bypass(struct ti_adpll_data *d)
0358 {
0359     unsigned long flags;
0360     u32 v;
0361 
0362     spin_lock_irqsave(&d->lock, flags);
0363     v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
0364     v &= ~BIT(ADPLL_CLKCTRL_IDLE);
0365     writel_relaxed(v, d->regs + ADPLL_CLKCTRL_OFFSET);
0366     spin_unlock_irqrestore(&d->lock, flags);
0367 }
0368 
0369 static bool ti_adpll_clock_is_bypass(struct ti_adpll_data *d)
0370 {
0371     u32 v;
0372 
0373     v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
0374 
0375     return v & BIT(ADPLL_STATUS_BYPASS);
0376 }
0377 
0378 /*
0379  * Locked and bypass are not actually mutually exclusive:  if you only care
0380  * about the DCO clock and not CLKOUT you can clear M2PWDNZ before enabling
0381  * the PLL, resulting in status (FREQLOCK | PHASELOCK | BYPASS) after lock.
0382  */
0383 static bool ti_adpll_is_locked(struct ti_adpll_data *d)
0384 {
0385     u32 v = readl_relaxed(d->regs + ADPLL_STATUS_OFFSET);
0386 
0387     return (v & ADPLL_STATUS_PREPARED_MASK) == ADPLL_STATUS_PREPARED_MASK;
0388 }
0389 
0390 static int ti_adpll_wait_lock(struct ti_adpll_data *d)
0391 {
0392     int retries = ADPLL_MAX_RETRIES;
0393 
0394     do {
0395         if (ti_adpll_is_locked(d))
0396             return 0;
0397         usleep_range(200, 300);
0398     } while (retries--);
0399 
0400     dev_err(d->dev, "pll failed to lock\n");
0401     return -ETIMEDOUT;
0402 }
0403 
0404 static int ti_adpll_prepare(struct clk_hw *hw)
0405 {
0406     struct ti_adpll_dco_data *dco = to_dco(hw);
0407     struct ti_adpll_data *d = to_adpll(dco);
0408 
0409     ti_adpll_clear_idle_bypass(d);
0410     ti_adpll_wait_lock(d);
0411 
0412     return 0;
0413 }
0414 
0415 static void ti_adpll_unprepare(struct clk_hw *hw)
0416 {
0417     struct ti_adpll_dco_data *dco = to_dco(hw);
0418     struct ti_adpll_data *d = to_adpll(dco);
0419 
0420     ti_adpll_set_idle_bypass(d);
0421 }
0422 
0423 static int ti_adpll_is_prepared(struct clk_hw *hw)
0424 {
0425     struct ti_adpll_dco_data *dco = to_dco(hw);
0426     struct ti_adpll_data *d = to_adpll(dco);
0427 
0428     return ti_adpll_is_locked(d);
0429 }
0430 
0431 /*
0432  * Note that the DCO clock is never subject to bypass: if the PLL is off,
0433  * dcoclk is low.
0434  */
0435 static unsigned long ti_adpll_recalc_rate(struct clk_hw *hw,
0436                       unsigned long parent_rate)
0437 {
0438     struct ti_adpll_dco_data *dco = to_dco(hw);
0439     struct ti_adpll_data *d = to_adpll(dco);
0440     u32 frac_m, divider, v;
0441     u64 rate;
0442     unsigned long flags;
0443 
0444     if (ti_adpll_clock_is_bypass(d))
0445         return 0;
0446 
0447     spin_lock_irqsave(&d->lock, flags);
0448     frac_m = readl_relaxed(d->regs + ADPLL_FRACDIV_OFFSET);
0449     frac_m &= ADPLL_FRACDIV_FRACTIONALM_MASK;
0450     rate = (u64)readw_relaxed(d->regs + ADPLL_MN2DIV_OFFSET) << 18;
0451     rate += frac_m;
0452     rate *= parent_rate;
0453     divider = (readw_relaxed(d->regs + ADPLL_M2NDIV_OFFSET) + 1) << 18;
0454     spin_unlock_irqrestore(&d->lock, flags);
0455 
0456     do_div(rate, divider);
0457 
0458     if (d->c->is_type_s) {
0459         v = readl_relaxed(d->regs + ADPLL_CLKCTRL_OFFSET);
0460         if (v & BIT(ADPLL_CLKCTRL_REGM4XEN_ADPLL_S))
0461             rate *= 4;
0462         rate *= 2;
0463     }
0464 
0465     return rate;
0466 }
0467 
0468 /* PLL parent is always clkinp, bypass only affects the children */
0469 static u8 ti_adpll_get_parent(struct clk_hw *hw)
0470 {
0471     return 0;
0472 }
0473 
0474 static const struct clk_ops ti_adpll_ops = {
0475     .prepare = ti_adpll_prepare,
0476     .unprepare = ti_adpll_unprepare,
0477     .is_prepared = ti_adpll_is_prepared,
0478     .recalc_rate = ti_adpll_recalc_rate,
0479     .get_parent = ti_adpll_get_parent,
0480 };
0481 
0482 static int ti_adpll_init_dco(struct ti_adpll_data *d)
0483 {
0484     struct clk_init_data init;
0485     struct clk *clock;
0486     const char *postfix;
0487     int width, err;
0488 
0489     d->outputs.clks = devm_kcalloc(d->dev,
0490                        MAX_ADPLL_OUTPUTS,
0491                        sizeof(struct clk *),
0492                        GFP_KERNEL);
0493     if (!d->outputs.clks)
0494         return -ENOMEM;
0495 
0496     if (d->c->output_index < 0)
0497         postfix = "dco";
0498     else
0499         postfix = NULL;
0500 
0501     init.name = ti_adpll_clk_get_name(d, d->c->output_index, postfix);
0502     if (!init.name)
0503         return -EINVAL;
0504 
0505     init.parent_names = d->parent_names;
0506     init.num_parents = d->c->nr_max_inputs;
0507     init.ops = &ti_adpll_ops;
0508     init.flags = CLK_GET_RATE_NOCACHE;
0509     d->dco.hw.init = &init;
0510 
0511     if (d->c->is_type_s)
0512         width = 5;
0513     else
0514         width = 4;
0515 
0516     /* Internal input clock divider N2 */
0517     err = ti_adpll_init_divider(d, TI_ADPLL_N2, -ENODEV, "n2",
0518                     d->parent_clocks[TI_ADPLL_CLKINP],
0519                     d->regs + ADPLL_MN2DIV_OFFSET,
0520                     ADPLL_MN2DIV_N2, width, 0);
0521     if (err)
0522         return err;
0523 
0524     clock = devm_clk_register(d->dev, &d->dco.hw);
0525     if (IS_ERR(clock))
0526         return PTR_ERR(clock);
0527 
0528     return ti_adpll_setup_clock(d, clock, TI_ADPLL_DCO, d->c->output_index,
0529                     init.name, NULL);
0530 }
0531 
0532 static int ti_adpll_clkout_enable(struct clk_hw *hw)
0533 {
0534     struct ti_adpll_clkout_data *co = to_clkout(hw);
0535     struct clk_hw *gate_hw = &co->gate.hw;
0536 
0537     __clk_hw_set_clk(gate_hw, hw);
0538 
0539     return clk_gate_ops.enable(gate_hw);
0540 }
0541 
0542 static void ti_adpll_clkout_disable(struct clk_hw *hw)
0543 {
0544     struct ti_adpll_clkout_data *co = to_clkout(hw);
0545     struct clk_hw *gate_hw = &co->gate.hw;
0546 
0547     __clk_hw_set_clk(gate_hw, hw);
0548     clk_gate_ops.disable(gate_hw);
0549 }
0550 
0551 static int ti_adpll_clkout_is_enabled(struct clk_hw *hw)
0552 {
0553     struct ti_adpll_clkout_data *co = to_clkout(hw);
0554     struct clk_hw *gate_hw = &co->gate.hw;
0555 
0556     __clk_hw_set_clk(gate_hw, hw);
0557 
0558     return clk_gate_ops.is_enabled(gate_hw);
0559 }
0560 
0561 /* Setting PLL bypass puts clkout and clkoutx2 into bypass */
0562 static u8 ti_adpll_clkout_get_parent(struct clk_hw *hw)
0563 {
0564     struct ti_adpll_clkout_data *co = to_clkout(hw);
0565     struct ti_adpll_data *d = co->adpll;
0566 
0567     return ti_adpll_clock_is_bypass(d);
0568 }
0569 
0570 static int ti_adpll_init_clkout(struct ti_adpll_data *d,
0571                 enum ti_adpll_clocks index,
0572                 int output_index, int gate_bit,
0573                 char *name, struct clk *clk0,
0574                 struct clk *clk1)
0575 {
0576     struct ti_adpll_clkout_data *co;
0577     struct clk_init_data init;
0578     struct clk_ops *ops;
0579     const char *parent_names[2];
0580     const char *child_name;
0581     struct clk *clock;
0582     int err;
0583 
0584     co = devm_kzalloc(d->dev, sizeof(*co), GFP_KERNEL);
0585     if (!co)
0586         return -ENOMEM;
0587     co->adpll = d;
0588 
0589     err = of_property_read_string_index(d->np,
0590                         "clock-output-names",
0591                         output_index,
0592                         &child_name);
0593     if (err)
0594         return err;
0595 
0596     ops = devm_kzalloc(d->dev, sizeof(*ops), GFP_KERNEL);
0597     if (!ops)
0598         return -ENOMEM;
0599 
0600     init.name = child_name;
0601     init.ops = ops;
0602     init.flags = 0;
0603     co->hw.init = &init;
0604     parent_names[0] = __clk_get_name(clk0);
0605     parent_names[1] = __clk_get_name(clk1);
0606     init.parent_names = parent_names;
0607     init.num_parents = 2;
0608 
0609     ops->get_parent = ti_adpll_clkout_get_parent;
0610     ops->determine_rate = __clk_mux_determine_rate;
0611     if (gate_bit) {
0612         co->gate.lock = &d->lock;
0613         co->gate.reg = d->regs + ADPLL_CLKCTRL_OFFSET;
0614         co->gate.bit_idx = gate_bit;
0615         ops->enable = ti_adpll_clkout_enable;
0616         ops->disable = ti_adpll_clkout_disable;
0617         ops->is_enabled = ti_adpll_clkout_is_enabled;
0618     }
0619 
0620     clock = devm_clk_register(d->dev, &co->hw);
0621     if (IS_ERR(clock)) {
0622         dev_err(d->dev, "failed to register output %s: %li\n",
0623             name, PTR_ERR(clock));
0624         return PTR_ERR(clock);
0625     }
0626 
0627     return ti_adpll_setup_clock(d, clock, index, output_index, child_name,
0628                     NULL);
0629 }
0630 
0631 static int ti_adpll_init_children_adpll_s(struct ti_adpll_data *d)
0632 {
0633     int err;
0634 
0635     if (!d->c->is_type_s)
0636         return 0;
0637 
0638     /* Internal mux, sources from divider N2 or clkinpulow */
0639     err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
0640                 d->clocks[TI_ADPLL_N2].clk,
0641                 d->parent_clocks[TI_ADPLL_CLKINPULOW],
0642                 d->regs + ADPLL_CLKCTRL_OFFSET,
0643                 ADPLL_CLKCTRL_ULOWCLKEN);
0644     if (err)
0645         return err;
0646 
0647     /* Internal divider M2, sources DCO */
0648     err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV, "m2",
0649                     d->clocks[TI_ADPLL_DCO].clk,
0650                     d->regs + ADPLL_M2NDIV_OFFSET,
0651                     ADPLL_M2NDIV_M2,
0652                     ADPLL_M2NDIV_M2_ADPLL_S_WIDTH,
0653                     CLK_DIVIDER_ONE_BASED);
0654     if (err)
0655         return err;
0656 
0657     /* Internal fixed divider, after M2 before clkout */
0658     err = ti_adpll_init_fixed_factor(d, TI_ADPLL_DIV2, "div2",
0659                      d->clocks[TI_ADPLL_M2].clk,
0660                      1, 2);
0661     if (err)
0662         return err;
0663 
0664     /* Output clkout with a mux and gate, sources from div2 or bypass */
0665     err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
0666                    ADPLL_CLKCTRL_CLKOUTEN, "clkout",
0667                    d->clocks[TI_ADPLL_DIV2].clk,
0668                    d->clocks[TI_ADPLL_BYPASS].clk);
0669     if (err)
0670         return err;
0671 
0672     /* Output clkoutx2 with a mux and gate, sources from M2 or bypass */
0673     err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT2, TI_ADPLL_S_CLKOUTX2, 0,
0674                    "clkout2", d->clocks[TI_ADPLL_M2].clk,
0675                    d->clocks[TI_ADPLL_BYPASS].clk);
0676     if (err)
0677         return err;
0678 
0679     /* Internal mux, sources from DCO and clkinphif */
0680     if (d->parent_clocks[TI_ADPLL_CLKINPHIF]) {
0681         err = ti_adpll_init_mux(d, TI_ADPLL_HIF, "hif",
0682                     d->clocks[TI_ADPLL_DCO].clk,
0683                     d->parent_clocks[TI_ADPLL_CLKINPHIF],
0684                     d->regs + ADPLL_CLKCTRL_OFFSET,
0685                     ADPLL_CLKINPHIFSEL_ADPLL_S);
0686         if (err)
0687             return err;
0688     }
0689 
0690     /* Output clkouthif with a divider M3, sources from hif */
0691     err = ti_adpll_init_divider(d, TI_ADPLL_M3, TI_ADPLL_S_CLKOUTHIF, "m3",
0692                     d->clocks[TI_ADPLL_HIF].clk,
0693                     d->regs + ADPLL_M3DIV_OFFSET,
0694                     ADPLL_M3DIV_M3,
0695                     ADPLL_M3DIV_M3_WIDTH,
0696                     CLK_DIVIDER_ONE_BASED);
0697     if (err)
0698         return err;
0699 
0700     /* Output clock dcoclkldo is the DCO */
0701 
0702     return 0;
0703 }
0704 
0705 static int ti_adpll_init_children_adpll_lj(struct ti_adpll_data *d)
0706 {
0707     int err;
0708 
0709     if (d->c->is_type_s)
0710         return 0;
0711 
0712     /* Output clkdcoldo, gated output of DCO */
0713     err = ti_adpll_init_gate(d, TI_ADPLL_DCO_GATE, TI_ADPLL_LJ_CLKDCOLDO,
0714                  "clkdcoldo", d->clocks[TI_ADPLL_DCO].clk,
0715                  d->regs + ADPLL_CLKCTRL_OFFSET,
0716                  ADPLL_CLKCTRL_CLKDCOLDOEN, 0);
0717     if (err)
0718         return err;
0719 
0720     /* Internal divider M2, sources from DCO */
0721     err = ti_adpll_init_divider(d, TI_ADPLL_M2, -ENODEV,
0722                     "m2", d->clocks[TI_ADPLL_DCO].clk,
0723                     d->regs + ADPLL_M2NDIV_OFFSET,
0724                     ADPLL_M2NDIV_M2,
0725                     ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH,
0726                     CLK_DIVIDER_ONE_BASED);
0727     if (err)
0728         return err;
0729 
0730     /* Output clkoutldo, gated output of M2 */
0731     err = ti_adpll_init_gate(d, TI_ADPLL_M2_GATE, TI_ADPLL_LJ_CLKOUTLDO,
0732                  "clkoutldo", d->clocks[TI_ADPLL_M2].clk,
0733                  d->regs + ADPLL_CLKCTRL_OFFSET,
0734                  ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ,
0735                  0);
0736     if (err)
0737         return err;
0738 
0739     /* Internal mux, sources from divider N2 or clkinpulow */
0740     err = ti_adpll_init_mux(d, TI_ADPLL_BYPASS, "bypass",
0741                 d->clocks[TI_ADPLL_N2].clk,
0742                 d->parent_clocks[TI_ADPLL_CLKINPULOW],
0743                 d->regs + ADPLL_CLKCTRL_OFFSET,
0744                 ADPLL_CLKCTRL_ULOWCLKEN);
0745     if (err)
0746         return err;
0747 
0748     /* Output clkout, sources M2 or bypass */
0749     err = ti_adpll_init_clkout(d, TI_ADPLL_CLKOUT, TI_ADPLL_S_CLKOUT,
0750                    ADPLL_CLKCTRL_CLKOUTEN, "clkout",
0751                    d->clocks[TI_ADPLL_M2].clk,
0752                    d->clocks[TI_ADPLL_BYPASS].clk);
0753     if (err)
0754         return err;
0755 
0756     return 0;
0757 }
0758 
0759 static void ti_adpll_free_resources(struct ti_adpll_data *d)
0760 {
0761     int i;
0762 
0763     for (i = TI_ADPLL_M3; i >= 0; i--) {
0764         struct ti_adpll_clock *ac = &d->clocks[i];
0765 
0766         if (!ac || IS_ERR_OR_NULL(ac->clk))
0767             continue;
0768         if (ac->cl)
0769             clkdev_drop(ac->cl);
0770         if (ac->unregister)
0771             ac->unregister(ac->clk);
0772     }
0773 }
0774 
0775 /* MPU PLL manages the lock register for all PLLs */
0776 static void ti_adpll_unlock_all(void __iomem *reg)
0777 {
0778     u32 v;
0779 
0780     v = readl_relaxed(reg);
0781     if (v == ADPLL_PLLSS_MMR_LOCK_ENABLED)
0782         writel_relaxed(ADPLL_PLLSS_MMR_UNLOCK_MAGIC, reg);
0783 }
0784 
0785 static int ti_adpll_init_registers(struct ti_adpll_data *d)
0786 {
0787     int register_offset = 0;
0788 
0789     if (d->c->is_type_s) {
0790         register_offset = 8;
0791         ti_adpll_unlock_all(d->iobase + ADPLL_PLLSS_MMR_LOCK_OFFSET);
0792     }
0793 
0794     d->regs = d->iobase + register_offset + ADPLL_PWRCTRL_OFFSET;
0795 
0796     return 0;
0797 }
0798 
0799 static int ti_adpll_init_inputs(struct ti_adpll_data *d)
0800 {
0801     static const char error[] = "need at least %i inputs";
0802     struct clk *clock;
0803     int nr_inputs;
0804 
0805     nr_inputs = of_clk_get_parent_count(d->np);
0806     if (nr_inputs < d->c->nr_max_inputs) {
0807         dev_err(d->dev, error, nr_inputs);
0808         return -EINVAL;
0809     }
0810     of_clk_parent_fill(d->np, d->parent_names, nr_inputs);
0811 
0812     clock = devm_clk_get(d->dev, d->parent_names[0]);
0813     if (IS_ERR(clock)) {
0814         dev_err(d->dev, "could not get clkinp\n");
0815         return PTR_ERR(clock);
0816     }
0817     d->parent_clocks[TI_ADPLL_CLKINP] = clock;
0818 
0819     clock = devm_clk_get(d->dev, d->parent_names[1]);
0820     if (IS_ERR(clock)) {
0821         dev_err(d->dev, "could not get clkinpulow clock\n");
0822         return PTR_ERR(clock);
0823     }
0824     d->parent_clocks[TI_ADPLL_CLKINPULOW] = clock;
0825 
0826     if (d->c->is_type_s) {
0827         clock =  devm_clk_get(d->dev, d->parent_names[2]);
0828         if (IS_ERR(clock)) {
0829             dev_err(d->dev, "could not get clkinphif clock\n");
0830             return PTR_ERR(clock);
0831         }
0832         d->parent_clocks[TI_ADPLL_CLKINPHIF] = clock;
0833     }
0834 
0835     return 0;
0836 }
0837 
0838 static const struct ti_adpll_platform_data ti_adpll_type_s = {
0839     .is_type_s = true,
0840     .nr_max_inputs = MAX_ADPLL_INPUTS,
0841     .nr_max_outputs = MAX_ADPLL_OUTPUTS,
0842     .output_index = TI_ADPLL_S_DCOCLKLDO,
0843 };
0844 
0845 static const struct ti_adpll_platform_data ti_adpll_type_lj = {
0846     .is_type_s = false,
0847     .nr_max_inputs = MAX_ADPLL_INPUTS - 1,
0848     .nr_max_outputs = MAX_ADPLL_OUTPUTS - 1,
0849     .output_index = -EINVAL,
0850 };
0851 
0852 static const struct of_device_id ti_adpll_match[] = {
0853     { .compatible = "ti,dm814-adpll-s-clock", &ti_adpll_type_s },
0854     { .compatible = "ti,dm814-adpll-lj-clock", &ti_adpll_type_lj },
0855     {},
0856 };
0857 MODULE_DEVICE_TABLE(of, ti_adpll_match);
0858 
0859 static int ti_adpll_probe(struct platform_device *pdev)
0860 {
0861     struct device_node *node = pdev->dev.of_node;
0862     struct device *dev = &pdev->dev;
0863     const struct of_device_id *match;
0864     const struct ti_adpll_platform_data *pdata;
0865     struct ti_adpll_data *d;
0866     struct resource *res;
0867     int err;
0868 
0869     match = of_match_device(ti_adpll_match, dev);
0870     if (match)
0871         pdata = match->data;
0872     else
0873         return -ENODEV;
0874 
0875     d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
0876     if (!d)
0877         return -ENOMEM;
0878     d->dev = dev;
0879     d->np = node;
0880     d->c = pdata;
0881     dev_set_drvdata(d->dev, d);
0882     spin_lock_init(&d->lock);
0883 
0884     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0885     if (!res)
0886         return -ENODEV;
0887     d->pa = res->start;
0888 
0889     d->iobase = devm_ioremap_resource(dev, res);
0890     if (IS_ERR(d->iobase))
0891         return PTR_ERR(d->iobase);
0892 
0893     err = ti_adpll_init_registers(d);
0894     if (err)
0895         return err;
0896 
0897     err = ti_adpll_init_inputs(d);
0898     if (err)
0899         return err;
0900 
0901     d->clocks = devm_kcalloc(d->dev,
0902                  TI_ADPLL_NR_CLOCKS,
0903                  sizeof(struct ti_adpll_clock),
0904                  GFP_KERNEL);
0905     if (!d->clocks)
0906         return -ENOMEM;
0907 
0908     err = ti_adpll_init_dco(d);
0909     if (err) {
0910         dev_err(dev, "could not register dco: %i\n", err);
0911         goto free;
0912     }
0913 
0914     err = ti_adpll_init_children_adpll_s(d);
0915     if (err)
0916         goto free;
0917     err = ti_adpll_init_children_adpll_lj(d);
0918     if (err)
0919         goto free;
0920 
0921     err = of_clk_add_provider(d->np, of_clk_src_onecell_get, &d->outputs);
0922     if (err)
0923         goto free;
0924 
0925     return 0;
0926 
0927 free:
0928     WARN_ON(1);
0929     ti_adpll_free_resources(d);
0930 
0931     return err;
0932 }
0933 
0934 static int ti_adpll_remove(struct platform_device *pdev)
0935 {
0936     struct ti_adpll_data *d = dev_get_drvdata(&pdev->dev);
0937 
0938     ti_adpll_free_resources(d);
0939 
0940     return 0;
0941 }
0942 
0943 static struct platform_driver ti_adpll_driver = {
0944     .driver = {
0945         .name = "ti-adpll",
0946         .of_match_table = ti_adpll_match,
0947     },
0948     .probe = ti_adpll_probe,
0949     .remove = ti_adpll_remove,
0950 };
0951 
0952 static int __init ti_adpll_init(void)
0953 {
0954     return platform_driver_register(&ti_adpll_driver);
0955 }
0956 core_initcall(ti_adpll_init);
0957 
0958 static void __exit ti_adpll_exit(void)
0959 {
0960     platform_driver_unregister(&ti_adpll_driver);
0961 }
0962 module_exit(ti_adpll_exit);
0963 
0964 MODULE_DESCRIPTION("Clock driver for dm814x ADPLL");
0965 MODULE_ALIAS("platform:dm814-adpll-clock");
0966 MODULE_AUTHOR("Tony LIndgren <tony@atomide.com>");
0967 MODULE_LICENSE("GPL v2");
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