clk/tegra/clk.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #include <linux/clkdev.h>
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/clk/tegra.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/reset-controller.h>
0017 #include <linux/string.h>
0018
0019 #include <soc/tegra/fuse.h>
0020
0021 #include "clk.h"
0022
0023 /* Global data of Tegra CPU CAR ops */
0024 static struct device_node *tegra_car_np;
0025 static struct tegra_cpu_car_ops dummy_car_ops;
0026 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
0027
0028 int *periph_clk_enb_refcnt;
0029 static int periph_banks;
0030 static u32 *periph_state_ctx;
0031 static struct clk **clks;
0032 static int clk_num;
0033 static struct clk_onecell_data clk_data;
0034
0035 /* Handlers for SoC-specific reset lines */
0036 static int (*special_reset_assert)(unsigned long);
0037 static int (*special_reset_deassert)(unsigned long);
0038 static unsigned int num_special_reset;
0039
0040 static const struct tegra_clk_periph_regs periph_regs[] = {
0041     [0] = {
0042         .enb_reg = CLK_OUT_ENB_L,
0043         .enb_set_reg = CLK_OUT_ENB_SET_L,
0044         .enb_clr_reg = CLK_OUT_ENB_CLR_L,
0045         .rst_reg = RST_DEVICES_L,
0046         .rst_set_reg = RST_DEVICES_SET_L,
0047         .rst_clr_reg = RST_DEVICES_CLR_L,
0048     },
0049     [1] = {
0050         .enb_reg = CLK_OUT_ENB_H,
0051         .enb_set_reg = CLK_OUT_ENB_SET_H,
0052         .enb_clr_reg = CLK_OUT_ENB_CLR_H,
0053         .rst_reg = RST_DEVICES_H,
0054         .rst_set_reg = RST_DEVICES_SET_H,
0055         .rst_clr_reg = RST_DEVICES_CLR_H,
0056     },
0057     [2] = {
0058         .enb_reg = CLK_OUT_ENB_U,
0059         .enb_set_reg = CLK_OUT_ENB_SET_U,
0060         .enb_clr_reg = CLK_OUT_ENB_CLR_U,
0061         .rst_reg = RST_DEVICES_U,
0062         .rst_set_reg = RST_DEVICES_SET_U,
0063         .rst_clr_reg = RST_DEVICES_CLR_U,
0064     },
0065     [3] = {
0066         .enb_reg = CLK_OUT_ENB_V,
0067         .enb_set_reg = CLK_OUT_ENB_SET_V,
0068         .enb_clr_reg = CLK_OUT_ENB_CLR_V,
0069         .rst_reg = RST_DEVICES_V,
0070         .rst_set_reg = RST_DEVICES_SET_V,
0071         .rst_clr_reg = RST_DEVICES_CLR_V,
0072     },
0073     [4] = {
0074         .enb_reg = CLK_OUT_ENB_W,
0075         .enb_set_reg = CLK_OUT_ENB_SET_W,
0076         .enb_clr_reg = CLK_OUT_ENB_CLR_W,
0077         .rst_reg = RST_DEVICES_W,
0078         .rst_set_reg = RST_DEVICES_SET_W,
0079         .rst_clr_reg = RST_DEVICES_CLR_W,
0080     },
0081     [5] = {
0082         .enb_reg = CLK_OUT_ENB_X,
0083         .enb_set_reg = CLK_OUT_ENB_SET_X,
0084         .enb_clr_reg = CLK_OUT_ENB_CLR_X,
0085         .rst_reg = RST_DEVICES_X,
0086         .rst_set_reg = RST_DEVICES_SET_X,
0087         .rst_clr_reg = RST_DEVICES_CLR_X,
0088     },
0089     [6] = {
0090         .enb_reg = CLK_OUT_ENB_Y,
0091         .enb_set_reg = CLK_OUT_ENB_SET_Y,
0092         .enb_clr_reg = CLK_OUT_ENB_CLR_Y,
0093         .rst_reg = RST_DEVICES_Y,
0094         .rst_set_reg = RST_DEVICES_SET_Y,
0095         .rst_clr_reg = RST_DEVICES_CLR_Y,
0096     },
0097 };
0098
0099 static void __iomem *clk_base;
0100
0101 static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
0102         unsigned long id)
0103 {
0104     /*
0105      * If peripheral is on the APB bus then we must read the APB bus to
0106      * flush the write operation in apb bus. This will avoid peripheral
0107      * access after disabling clock. Since the reset driver has no
0108      * knowledge of which reset IDs represent which devices, simply do
0109      * this all the time.
0110      */
0111     tegra_read_chipid();
0112
0113     if (id < periph_banks * 32) {
0114         writel_relaxed(BIT(id % 32),
0115                    clk_base + periph_regs[id / 32].rst_set_reg);
0116         return 0;
0117     } else if (id < periph_banks * 32 + num_special_reset) {
0118         return special_reset_assert(id);
0119     }
0120
0121     return -EINVAL;
0122 }
0123
0124 static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
0125         unsigned long id)
0126 {
0127     if (id < periph_banks * 32) {
0128         writel_relaxed(BIT(id % 32),
0129                    clk_base + periph_regs[id / 32].rst_clr_reg);
0130         return 0;
0131     } else if (id < periph_banks * 32 + num_special_reset) {
0132         return special_reset_deassert(id);
0133     }
0134
0135     return -EINVAL;
0136 }
0137
0138 static int tegra_clk_rst_reset(struct reset_controller_dev *rcdev,
0139         unsigned long id)
0140 {
0141     int err;
0142
0143     err = tegra_clk_rst_assert(rcdev, id);
0144     if (err)
0145         return err;
0146
0147     udelay(1);
0148
0149     return tegra_clk_rst_deassert(rcdev, id);
0150 }
0151
0152 const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
0153 {
0154     int reg_bank = clkid / 32;
0155
0156     if (reg_bank < periph_banks)
0157         return &periph_regs[reg_bank];
0158     else {
0159         WARN_ON(1);
0160         return NULL;
0161     }
0162 }
0163
0164 void tegra_clk_set_pllp_out_cpu(bool enable)
0165 {
0166     u32 val;
0167
0168     val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
0169     if (enable)
0170         val |= CLK_ENB_PLLP_OUT_CPU;
0171     else
0172         val &= ~CLK_ENB_PLLP_OUT_CPU;
0173
0174     writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
0175 }
0176
0177 void tegra_clk_periph_suspend(void)
0178 {
0179     unsigned int i, idx;
0180
0181     idx = 0;
0182     for (i = 0; i < periph_banks; i++, idx++)
0183         periph_state_ctx[idx] =
0184             readl_relaxed(clk_base + periph_regs[i].enb_reg);
0185
0186     for (i = 0; i < periph_banks; i++, idx++)
0187         periph_state_ctx[idx] =
0188             readl_relaxed(clk_base + periph_regs[i].rst_reg);
0189 }
0190
0191 void tegra_clk_periph_resume(void)
0192 {
0193     unsigned int i, idx;
0194
0195     idx = 0;
0196     for (i = 0; i < periph_banks; i++, idx++)
0197         writel_relaxed(periph_state_ctx[idx],
0198                    clk_base + periph_regs[i].enb_reg);
0199     /*
0200      * All non-boot peripherals will be in reset state on resume.
0201      * Wait for 5us of reset propagation delay before de-asserting
0202      * the peripherals based on the saved context.
0203      */
0204     fence_udelay(5, clk_base);
0205
0206     for (i = 0; i < periph_banks; i++, idx++)
0207         writel_relaxed(periph_state_ctx[idx],
0208                    clk_base + periph_regs[i].rst_reg);
0209
0210     fence_udelay(2, clk_base);
0211 }
0212
0213 static int tegra_clk_periph_ctx_init(int banks)
0214 {
0215     periph_state_ctx = kcalloc(2 * banks, sizeof(*periph_state_ctx),
0216                    GFP_KERNEL);
0217     if (!periph_state_ctx)
0218         return -ENOMEM;
0219
0220     return 0;
0221 }
0222
0223 struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
0224 {
0225     clk_base = regs;
0226
0227     if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
0228         return NULL;
0229
0230     periph_clk_enb_refcnt = kcalloc(32 * banks,
0231                     sizeof(*periph_clk_enb_refcnt),
0232                     GFP_KERNEL);
0233     if (!periph_clk_enb_refcnt)
0234         return NULL;
0235
0236     periph_banks = banks;
0237
0238     clks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);
0239     if (!clks) {
0240         kfree(periph_clk_enb_refcnt);
0241         return NULL;
0242     }
0243
0244     clk_num = num;
0245
0246     if (IS_ENABLED(CONFIG_PM_SLEEP)) {
0247         if (tegra_clk_periph_ctx_init(banks)) {
0248             kfree(periph_clk_enb_refcnt);
0249             kfree(clks);
0250             return NULL;
0251         }
0252     }
0253
0254     return clks;
0255 }
0256
0257 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
0258                 struct clk *clks[], int clk_max)
0259 {
0260     struct clk *clk;
0261
0262     for (; dup_list->clk_id < clk_max; dup_list++) {
0263         clk = clks[dup_list->clk_id];
0264         dup_list->lookup.clk = clk;
0265         clkdev_add(&dup_list->lookup);
0266     }
0267 }
0268
0269 void tegra_init_from_table(struct tegra_clk_init_table *tbl,
0270                struct clk *clks[], int clk_max)
0271 {
0272     struct clk *clk;
0273
0274     for (; tbl->clk_id < clk_max; tbl++) {
0275         clk = clks[tbl->clk_id];
0276         if (IS_ERR_OR_NULL(clk)) {
0277             pr_err("%s: invalid entry %ld in clks array for id %d\n",
0278                    __func__, PTR_ERR(clk), tbl->clk_id);
0279             WARN_ON(1);
0280
0281             continue;
0282         }
0283
0284         if (tbl->parent_id < clk_max) {
0285             struct clk *parent = clks[tbl->parent_id];
0286             if (clk_set_parent(clk, parent)) {
0287                 pr_err("%s: Failed to set parent %s of %s\n",
0288                        __func__, __clk_get_name(parent),
0289                        __clk_get_name(clk));
0290                 WARN_ON(1);
0291             }
0292         }
0293
0294         if (tbl->rate)
0295             if (clk_set_rate(clk, tbl->rate)) {
0296                 pr_err("%s: Failed to set rate %lu of %s\n",
0297                        __func__, tbl->rate,
0298                        __clk_get_name(clk));
0299                 WARN_ON(1);
0300             }
0301
0302         if (tbl->state)
0303             if (clk_prepare_enable(clk)) {
0304                 pr_err("%s: Failed to enable %s\n", __func__,
0305                        __clk_get_name(clk));
0306                 WARN_ON(1);
0307             }
0308     }
0309 }
0310
0311 static const struct reset_control_ops rst_ops = {
0312     .assert = tegra_clk_rst_assert,
0313     .deassert = tegra_clk_rst_deassert,
0314     .reset = tegra_clk_rst_reset,
0315 };
0316
0317 static struct reset_controller_dev rst_ctlr = {
0318     .ops = &rst_ops,
0319     .owner = THIS_MODULE,
0320     .of_reset_n_cells = 1,
0321 };
0322
0323 void __init tegra_add_of_provider(struct device_node *np,
0324                   void *clk_src_onecell_get)
0325 {
0326     int i;
0327
0328     tegra_car_np = np;
0329
0330     for (i = 0; i < clk_num; i++) {
0331         if (IS_ERR(clks[i])) {
0332             pr_err
0333                 ("Tegra clk %d: register failed with %ld\n",
0334                  i, PTR_ERR(clks[i]));
0335         }
0336         if (!clks[i])
0337             clks[i] = ERR_PTR(-EINVAL);
0338     }
0339
0340     clk_data.clks = clks;
0341     clk_data.clk_num = clk_num;
0342     of_clk_add_provider(np, clk_src_onecell_get, &clk_data);
0343
0344     rst_ctlr.of_node = np;
0345     rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset;
0346     reset_controller_register(&rst_ctlr);
0347 }
0348
0349 void __init tegra_init_special_resets(unsigned int num,
0350                       int (*assert)(unsigned long),
0351                       int (*deassert)(unsigned long))
0352 {
0353     num_special_reset = num;
0354     special_reset_assert = assert;
0355     special_reset_deassert = deassert;
0356 }
0357
0358 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
0359 {
0360     int i;
0361
0362     for (i = 0; i < num; i++, dev_clks++)
0363         clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
0364                 dev_clks->dev_id);
0365
0366     for (i = 0; i < clk_num; i++) {
0367         if (!IS_ERR_OR_NULL(clks[i]))
0368             clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
0369                 "tegra-clk-debug");
0370     }
0371 }
0372
0373 struct clk ** __init tegra_lookup_dt_id(int clk_id,
0374                     struct tegra_clk *tegra_clk)
0375 {
0376     if (tegra_clk[clk_id].present)
0377         return &clks[tegra_clk[clk_id].dt_id];
0378     else
0379         return NULL;
0380 }
0381
0382 static struct device_node *tegra_clk_get_of_node(struct clk_hw *hw)
0383 {
0384     struct device_node *np;
0385     char *node_name;
0386
0387     node_name = kstrdup(hw->init->name, GFP_KERNEL);
0388     if (!node_name)
0389         return NULL;
0390
0391     strreplace(node_name, '_', '-');
0392
0393     for_each_child_of_node(tegra_car_np, np) {
0394         if (!strcmp(np->name, node_name))
0395             break;
0396     }
0397
0398     kfree(node_name);
0399
0400     return np;
0401 }
0402
0403 struct clk *tegra_clk_dev_register(struct clk_hw *hw)
0404 {
0405     struct platform_device *pdev, *parent;
0406     const char *dev_name = NULL;
0407     struct device *dev = NULL;
0408     struct device_node *np;
0409
0410     np = tegra_clk_get_of_node(hw);
0411
0412     if (!of_device_is_available(np))
0413         goto put_node;
0414
0415     dev_name = kasprintf(GFP_KERNEL, "tegra_clk_%s", hw->init->name);
0416     if (!dev_name)
0417         goto put_node;
0418
0419     parent = of_find_device_by_node(tegra_car_np);
0420     if (parent) {
0421         pdev = of_platform_device_create(np, dev_name, &parent->dev);
0422         put_device(&parent->dev);
0423
0424         if (!pdev) {
0425             pr_err("%s: failed to create device for %pOF\n",
0426                    __func__, np);
0427             goto free_name;
0428         }
0429
0430         dev = &pdev->dev;
0431         pm_runtime_enable(dev);
0432     } else {
0433         WARN(1, "failed to find device for %pOF\n", tegra_car_np);
0434     }
0435
0436 free_name:
0437     kfree(dev_name);
0438 put_node:
0439     of_node_put(np);
0440
0441     return clk_register(dev, hw);
0442 }
0443
0444 tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
0445
0446 static int __init tegra_clocks_apply_init_table(void)
0447 {
0448     if (!tegra_clk_apply_init_table)
0449         return 0;
0450
0451     tegra_clk_apply_init_table();
0452
0453     return 0;
0454 }
0455 arch_initcall(tegra_clocks_apply_init_table);