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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/io.h>
0007 #include <linux/delay.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/init.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/clk/tegra.h>
0016 
0017 #include <soc/tegra/pmc.h>
0018 
0019 #include <dt-bindings/clock/tegra30-car.h>
0020 
0021 #include "clk.h"
0022 #include "clk-id.h"
0023 
0024 #define OSC_CTRL            0x50
0025 #define OSC_CTRL_OSC_FREQ_MASK      (0xF<<28)
0026 #define OSC_CTRL_OSC_FREQ_13MHZ     (0X0<<28)
0027 #define OSC_CTRL_OSC_FREQ_19_2MHZ   (0X4<<28)
0028 #define OSC_CTRL_OSC_FREQ_12MHZ     (0X8<<28)
0029 #define OSC_CTRL_OSC_FREQ_26MHZ     (0XC<<28)
0030 #define OSC_CTRL_OSC_FREQ_16_8MHZ   (0X1<<28)
0031 #define OSC_CTRL_OSC_FREQ_38_4MHZ   (0X5<<28)
0032 #define OSC_CTRL_OSC_FREQ_48MHZ     (0X9<<28)
0033 #define OSC_CTRL_MASK           (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
0034 
0035 #define OSC_CTRL_PLL_REF_DIV_MASK   (3<<26)
0036 #define OSC_CTRL_PLL_REF_DIV_1      (0<<26)
0037 #define OSC_CTRL_PLL_REF_DIV_2      (1<<26)
0038 #define OSC_CTRL_PLL_REF_DIV_4      (2<<26)
0039 
0040 #define OSC_FREQ_DET            0x58
0041 #define OSC_FREQ_DET_TRIG       BIT(31)
0042 
0043 #define OSC_FREQ_DET_STATUS     0x5c
0044 #define OSC_FREQ_DET_BUSY       BIT(31)
0045 #define OSC_FREQ_DET_CNT_MASK       0xffff
0046 
0047 #define CCLKG_BURST_POLICY 0x368
0048 #define SUPER_CCLKG_DIVIDER 0x36c
0049 #define CCLKLP_BURST_POLICY 0x370
0050 #define SUPER_CCLKLP_DIVIDER 0x374
0051 #define SCLK_BURST_POLICY 0x028
0052 #define SUPER_SCLK_DIVIDER 0x02c
0053 
0054 #define SYSTEM_CLK_RATE 0x030
0055 
0056 #define TEGRA30_CLK_PERIPH_BANKS    5
0057 
0058 #define PLLC_BASE 0x80
0059 #define PLLC_MISC 0x8c
0060 #define PLLM_BASE 0x90
0061 #define PLLM_MISC 0x9c
0062 #define PLLP_BASE 0xa0
0063 #define PLLP_MISC 0xac
0064 #define PLLX_BASE 0xe0
0065 #define PLLX_MISC 0xe4
0066 #define PLLD_BASE 0xd0
0067 #define PLLD_MISC 0xdc
0068 #define PLLD2_BASE 0x4b8
0069 #define PLLD2_MISC 0x4bc
0070 #define PLLE_BASE 0xe8
0071 #define PLLE_MISC 0xec
0072 #define PLLA_BASE 0xb0
0073 #define PLLA_MISC 0xbc
0074 #define PLLU_BASE 0xc0
0075 #define PLLU_MISC 0xcc
0076 
0077 #define PLL_MISC_LOCK_ENABLE 18
0078 #define PLLDU_MISC_LOCK_ENABLE 22
0079 #define PLLE_MISC_LOCK_ENABLE 9
0080 
0081 #define PLL_BASE_LOCK BIT(27)
0082 #define PLLE_MISC_LOCK BIT(11)
0083 
0084 #define PLLE_AUX 0x48c
0085 #define PLLC_OUT 0x84
0086 #define PLLM_OUT 0x94
0087 #define PLLP_OUTA 0xa4
0088 #define PLLP_OUTB 0xa8
0089 #define PLLA_OUT 0xb4
0090 
0091 #define AUDIO_SYNC_CLK_I2S0 0x4a0
0092 #define AUDIO_SYNC_CLK_I2S1 0x4a4
0093 #define AUDIO_SYNC_CLK_I2S2 0x4a8
0094 #define AUDIO_SYNC_CLK_I2S3 0x4ac
0095 #define AUDIO_SYNC_CLK_I2S4 0x4b0
0096 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
0097 
0098 #define CLK_SOURCE_SPDIF_OUT 0x108
0099 #define CLK_SOURCE_PWM 0x110
0100 #define CLK_SOURCE_D_AUDIO 0x3d0
0101 #define CLK_SOURCE_DAM0 0x3d8
0102 #define CLK_SOURCE_DAM1 0x3dc
0103 #define CLK_SOURCE_DAM2 0x3e0
0104 #define CLK_SOURCE_3D2 0x3b0
0105 #define CLK_SOURCE_2D 0x15c
0106 #define CLK_SOURCE_HDMI 0x18c
0107 #define CLK_SOURCE_DSIB 0xd0
0108 #define CLK_SOURCE_SE 0x42c
0109 #define CLK_SOURCE_EMC 0x19c
0110 
0111 #define AUDIO_SYNC_DOUBLER 0x49c
0112 
0113 /* Tegra CPU clock and reset control regs */
0114 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX      0x4c
0115 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET  0x340
0116 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR  0x344
0117 #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR    0x34c
0118 #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
0119 
0120 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
0121 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
0122 
0123 #define CLK_RESET_CCLK_BURST    0x20
0124 #define CLK_RESET_CCLK_DIVIDER  0x24
0125 #define CLK_RESET_PLLX_BASE 0xe0
0126 #define CLK_RESET_PLLX_MISC 0xe4
0127 
0128 #define CLK_RESET_SOURCE_CSITE  0x1d4
0129 
0130 #define CLK_RESET_CCLK_BURST_POLICY_SHIFT   28
0131 #define CLK_RESET_CCLK_RUN_POLICY_SHIFT     4
0132 #define CLK_RESET_CCLK_IDLE_POLICY_SHIFT    0
0133 #define CLK_RESET_CCLK_IDLE_POLICY      1
0134 #define CLK_RESET_CCLK_RUN_POLICY       2
0135 #define CLK_RESET_CCLK_BURST_POLICY_PLLX    8
0136 
0137 /* PLLM override registers */
0138 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
0139 
0140 #ifdef CONFIG_PM_SLEEP
0141 static struct cpu_clk_suspend_context {
0142     u32 pllx_misc;
0143     u32 pllx_base;
0144 
0145     u32 cpu_burst;
0146     u32 clk_csite_src;
0147     u32 cclk_divider;
0148 } tegra30_cpu_clk_sctx;
0149 #endif
0150 
0151 static void __iomem *clk_base;
0152 static void __iomem *pmc_base;
0153 static unsigned long input_freq;
0154 
0155 static DEFINE_SPINLOCK(cml_lock);
0156 static DEFINE_SPINLOCK(pll_d_lock);
0157 
0158 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,   \
0159                 _clk_num, _gate_flags, _clk_id) \
0160     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0161             30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
0162             _clk_num, _gate_flags, _clk_id)
0163 
0164 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
0165                  _clk_num, _gate_flags, _clk_id)    \
0166     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0167             29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
0168             _clk_num, _gate_flags, _clk_id)
0169 
0170 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset,   \
0171                 _clk_num, _gate_flags, _clk_id) \
0172     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0173             30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT |      \
0174             TEGRA_DIVIDER_ROUND_UP, _clk_num,   \
0175             _gate_flags, _clk_id)
0176 
0177 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
0178                   _mux_shift, _mux_width, _clk_num, \
0179                   _gate_flags, _clk_id)         \
0180     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0181             _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
0182             _clk_num, _gate_flags,  \
0183             _clk_id)
0184 
0185 static struct clk **clks;
0186 
0187 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
0188     { 12000000, 1040000000, 520,  6, 1, 8 },
0189     { 13000000, 1040000000, 480,  6, 1, 8 },
0190     { 16800000, 1040000000, 495,  8, 1, 8 }, /* actual: 1039.5 MHz */
0191     { 19200000, 1040000000, 325,  6, 1, 6 },
0192     { 26000000, 1040000000, 520, 13, 1, 8 },
0193     { 12000000,  832000000, 416,  6, 1, 8 },
0194     { 13000000,  832000000, 832, 13, 1, 8 },
0195     { 16800000,  832000000, 396,  8, 1, 8 }, /* actual: 831.6 MHz */
0196     { 19200000,  832000000, 260,  6, 1, 8 },
0197     { 26000000,  832000000, 416, 13, 1, 8 },
0198     { 12000000,  624000000, 624, 12, 1, 8 },
0199     { 13000000,  624000000, 624, 13, 1, 8 },
0200     { 16800000,  600000000, 520, 14, 1, 8 },
0201     { 19200000,  624000000, 520, 16, 1, 8 },
0202     { 26000000,  624000000, 624, 26, 1, 8 },
0203     { 12000000,  600000000, 600, 12, 1, 8 },
0204     { 13000000,  600000000, 600, 13, 1, 8 },
0205     { 16800000,  600000000, 500, 14, 1, 8 },
0206     { 19200000,  600000000, 375, 12, 1, 6 },
0207     { 26000000,  600000000, 600, 26, 1, 8 },
0208     { 12000000,  520000000, 520, 12, 1, 8 },
0209     { 13000000,  520000000, 520, 13, 1, 8 },
0210     { 16800000,  520000000, 495, 16, 1, 8 }, /* actual: 519.75 MHz */
0211     { 19200000,  520000000, 325, 12, 1, 6 },
0212     { 26000000,  520000000, 520, 26, 1, 8 },
0213     { 12000000,  416000000, 416, 12, 1, 8 },
0214     { 13000000,  416000000, 416, 13, 1, 8 },
0215     { 16800000,  416000000, 396, 16, 1, 8 }, /* actual: 415.8 MHz */
0216     { 19200000,  416000000, 260, 12, 1, 6 },
0217     { 26000000,  416000000, 416, 26, 1, 8 },
0218     {        0,          0,   0,  0, 0, 0 },
0219 };
0220 
0221 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
0222     { 12000000, 666000000, 666, 12, 1, 8 },
0223     { 13000000, 666000000, 666, 13, 1, 8 },
0224     { 16800000, 666000000, 555, 14, 1, 8 },
0225     { 19200000, 666000000, 555, 16, 1, 8 },
0226     { 26000000, 666000000, 666, 26, 1, 8 },
0227     { 12000000, 600000000, 600, 12, 1, 8 },
0228     { 13000000, 600000000, 600, 13, 1, 8 },
0229     { 16800000, 600000000, 500, 14, 1, 8 },
0230     { 19200000, 600000000, 375, 12, 1, 6 },
0231     { 26000000, 600000000, 600, 26, 1, 8 },
0232     {        0,         0,   0,  0, 0, 0 },
0233 };
0234 
0235 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
0236     { 12000000, 216000000, 432, 12, 2, 8 },
0237     { 13000000, 216000000, 432, 13, 2, 8 },
0238     { 16800000, 216000000, 360, 14, 2, 8 },
0239     { 19200000, 216000000, 360, 16, 2, 8 },
0240     { 26000000, 216000000, 432, 26, 2, 8 },
0241     {        0,         0,   0,  0, 0, 0 },
0242 };
0243 
0244 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
0245     {  9600000, 564480000, 294,  5, 1, 4 },
0246     {  9600000, 552960000, 288,  5, 1, 4 },
0247     {  9600000,  24000000,   5,  2, 1, 1 },
0248     { 28800000,  56448000,  49, 25, 1, 1 },
0249     { 28800000,  73728000,  64, 25, 1, 1 },
0250     { 28800000,  24000000,   5,  6, 1, 1 },
0251     {        0,         0,   0,  0, 0, 0 },
0252 };
0253 
0254 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
0255     { 12000000,  216000000,  216, 12, 1,  4 },
0256     { 13000000,  216000000,  216, 13, 1,  4 },
0257     { 16800000,  216000000,  180, 14, 1,  4 },
0258     { 19200000,  216000000,  180, 16, 1,  4 },
0259     { 26000000,  216000000,  216, 26, 1,  4 },
0260     { 12000000,  594000000,  594, 12, 1,  8 },
0261     { 13000000,  594000000,  594, 13, 1,  8 },
0262     { 16800000,  594000000,  495, 14, 1,  8 },
0263     { 19200000,  594000000,  495, 16, 1,  8 },
0264     { 26000000,  594000000,  594, 26, 1,  8 },
0265     { 12000000, 1000000000, 1000, 12, 1, 12 },
0266     { 13000000, 1000000000, 1000, 13, 1, 12 },
0267     { 19200000, 1000000000,  625, 12, 1,  8 },
0268     { 26000000, 1000000000, 1000, 26, 1, 12 },
0269     {        0,          0,    0,  0, 0,  0 },
0270 };
0271 
0272 static const struct pdiv_map pllu_p[] = {
0273     { .pdiv = 1, .hw_val = 1 },
0274     { .pdiv = 2, .hw_val = 0 },
0275     { .pdiv = 0, .hw_val = 0 },
0276 };
0277 
0278 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
0279     { 12000000, 480000000, 960, 12, 2, 12 },
0280     { 13000000, 480000000, 960, 13, 2, 12 },
0281     { 16800000, 480000000, 400,  7, 2,  5 },
0282     { 19200000, 480000000, 200,  4, 2,  3 },
0283     { 26000000, 480000000, 960, 26, 2, 12 },
0284     {        0,         0,   0,  0, 0,  0 },
0285 };
0286 
0287 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
0288     /* 1.7 GHz */
0289     { 12000000, 1700000000, 850,   6, 1, 8 },
0290     { 13000000, 1700000000, 915,   7, 1, 8 }, /* actual: 1699.2 MHz */
0291     { 16800000, 1700000000, 708,   7, 1, 8 }, /* actual: 1699.2 MHz */
0292     { 19200000, 1700000000, 885,  10, 1, 8 }, /* actual: 1699.2 MHz */
0293     { 26000000, 1700000000, 850,  13, 1, 8 },
0294     /* 1.6 GHz */
0295     { 12000000, 1600000000, 800,   6, 1, 8 },
0296     { 13000000, 1600000000, 738,   6, 1, 8 }, /* actual: 1599.0 MHz */
0297     { 16800000, 1600000000, 857,   9, 1, 8 }, /* actual: 1599.7 MHz */
0298     { 19200000, 1600000000, 500,   6, 1, 8 },
0299     { 26000000, 1600000000, 800,  13, 1, 8 },
0300     /* 1.5 GHz */
0301     { 12000000, 1500000000, 750,   6, 1, 8 },
0302     { 13000000, 1500000000, 923,   8, 1, 8 }, /* actual: 1499.8 MHz */
0303     { 16800000, 1500000000, 625,   7, 1, 8 },
0304     { 19200000, 1500000000, 625,   8, 1, 8 },
0305     { 26000000, 1500000000, 750,  13, 1, 8 },
0306     /* 1.4 GHz */
0307     { 12000000, 1400000000,  700,  6, 1, 8 },
0308     { 13000000, 1400000000,  969,  9, 1, 8 }, /* actual: 1399.7 MHz */
0309     { 16800000, 1400000000, 1000, 12, 1, 8 },
0310     { 19200000, 1400000000,  875, 12, 1, 8 },
0311     { 26000000, 1400000000,  700, 13, 1, 8 },
0312     /* 1.3 GHz */
0313     { 12000000, 1300000000,  975,  9, 1, 8 },
0314     { 13000000, 1300000000, 1000, 10, 1, 8 },
0315     { 16800000, 1300000000,  928, 12, 1, 8 }, /* actual: 1299.2 MHz */
0316     { 19200000, 1300000000,  812, 12, 1, 8 }, /* actual: 1299.2 MHz */
0317     { 26000000, 1300000000,  650, 13, 1, 8 },
0318     /* 1.2 GHz */
0319     { 12000000, 1200000000, 1000, 10, 1, 8 },
0320     { 13000000, 1200000000,  923, 10, 1, 8 }, /* actual: 1199.9 MHz */
0321     { 16800000, 1200000000, 1000, 14, 1, 8 },
0322     { 19200000, 1200000000, 1000, 16, 1, 8 },
0323     { 26000000, 1200000000,  600, 13, 1, 8 },
0324     /* 1.1 GHz */
0325     { 12000000, 1100000000, 825,   9, 1, 8 },
0326     { 13000000, 1100000000, 846,  10, 1, 8 }, /* actual: 1099.8 MHz */
0327     { 16800000, 1100000000, 982,  15, 1, 8 }, /* actual: 1099.8 MHz */
0328     { 19200000, 1100000000, 859,  15, 1, 8 }, /* actual: 1099.5 MHz */
0329     { 26000000, 1100000000, 550,  13, 1, 8 },
0330     /* 1 GHz */
0331     { 12000000, 1000000000, 1000, 12, 1, 8 },
0332     { 13000000, 1000000000, 1000, 13, 1, 8 },
0333     { 16800000, 1000000000,  833, 14, 1, 8 }, /* actual: 999.6 MHz */
0334     { 19200000, 1000000000,  625, 12, 1, 8 },
0335     { 26000000, 1000000000, 1000, 26, 1, 8 },
0336     {        0,          0,    0,  0, 0, 0 },
0337 };
0338 
0339 static const struct pdiv_map plle_p[] = {
0340     { .pdiv = 18, .hw_val = 18 },
0341     { .pdiv = 24, .hw_val = 24 },
0342     { .pdiv =  0, .hw_val =  0 },
0343 };
0344 
0345 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
0346     /* PLLE special case: use cpcon field to store cml divider value */
0347     {  12000000, 100000000, 150,  1, 18, 11 },
0348     { 216000000, 100000000, 200, 18, 24, 13 },
0349     {         0,         0,   0,  0,  0,  0 },
0350 };
0351 
0352 /* PLL parameters */
0353 static struct tegra_clk_pll_params pll_c_params __ro_after_init = {
0354     .input_min = 2000000,
0355     .input_max = 31000000,
0356     .cf_min = 1000000,
0357     .cf_max = 6000000,
0358     .vco_min = 20000000,
0359     .vco_max = 1400000000,
0360     .base_reg = PLLC_BASE,
0361     .misc_reg = PLLC_MISC,
0362     .lock_mask = PLL_BASE_LOCK,
0363     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0364     .lock_delay = 300,
0365     .freq_table = pll_c_freq_table,
0366     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
0367          TEGRA_PLL_HAS_LOCK_ENABLE,
0368 };
0369 
0370 static struct div_nmp pllm_nmp = {
0371     .divn_shift = 8,
0372     .divn_width = 10,
0373     .override_divn_shift = 5,
0374     .divm_shift = 0,
0375     .divm_width = 5,
0376     .override_divm_shift = 0,
0377     .divp_shift = 20,
0378     .divp_width = 3,
0379     .override_divp_shift = 15,
0380 };
0381 
0382 static struct tegra_clk_pll_params pll_m_params __ro_after_init = {
0383     .input_min = 2000000,
0384     .input_max = 31000000,
0385     .cf_min = 1000000,
0386     .cf_max = 6000000,
0387     .vco_min = 20000000,
0388     .vco_max = 1200000000,
0389     .base_reg = PLLM_BASE,
0390     .misc_reg = PLLM_MISC,
0391     .lock_mask = PLL_BASE_LOCK,
0392     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0393     .lock_delay = 300,
0394     .div_nmp = &pllm_nmp,
0395     .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
0396     .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
0397     .freq_table = pll_m_freq_table,
0398     .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
0399          TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
0400          TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
0401 };
0402 
0403 static struct tegra_clk_pll_params pll_p_params __ro_after_init = {
0404     .input_min = 2000000,
0405     .input_max = 31000000,
0406     .cf_min = 1000000,
0407     .cf_max = 6000000,
0408     .vco_min = 20000000,
0409     .vco_max = 1400000000,
0410     .base_reg = PLLP_BASE,
0411     .misc_reg = PLLP_MISC,
0412     .lock_mask = PLL_BASE_LOCK,
0413     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0414     .lock_delay = 300,
0415     .freq_table = pll_p_freq_table,
0416     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
0417          TEGRA_PLL_HAS_LOCK_ENABLE,
0418     .fixed_rate = 408000000,
0419 };
0420 
0421 static struct tegra_clk_pll_params pll_a_params = {
0422     .input_min = 2000000,
0423     .input_max = 31000000,
0424     .cf_min = 1000000,
0425     .cf_max = 6000000,
0426     .vco_min = 20000000,
0427     .vco_max = 1400000000,
0428     .base_reg = PLLA_BASE,
0429     .misc_reg = PLLA_MISC,
0430     .lock_mask = PLL_BASE_LOCK,
0431     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0432     .lock_delay = 300,
0433     .freq_table = pll_a_freq_table,
0434     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
0435          TEGRA_PLL_HAS_LOCK_ENABLE,
0436 };
0437 
0438 static struct tegra_clk_pll_params pll_d_params __ro_after_init = {
0439     .input_min = 2000000,
0440     .input_max = 40000000,
0441     .cf_min = 1000000,
0442     .cf_max = 6000000,
0443     .vco_min = 40000000,
0444     .vco_max = 1000000000,
0445     .base_reg = PLLD_BASE,
0446     .misc_reg = PLLD_MISC,
0447     .lock_mask = PLL_BASE_LOCK,
0448     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0449     .lock_delay = 1000,
0450     .freq_table = pll_d_freq_table,
0451     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0452          TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0453 };
0454 
0455 static struct tegra_clk_pll_params pll_d2_params __ro_after_init = {
0456     .input_min = 2000000,
0457     .input_max = 40000000,
0458     .cf_min = 1000000,
0459     .cf_max = 6000000,
0460     .vco_min = 40000000,
0461     .vco_max = 1000000000,
0462     .base_reg = PLLD2_BASE,
0463     .misc_reg = PLLD2_MISC,
0464     .lock_mask = PLL_BASE_LOCK,
0465     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0466     .lock_delay = 1000,
0467     .freq_table = pll_d_freq_table,
0468     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0469          TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0470 };
0471 
0472 static struct tegra_clk_pll_params pll_u_params __ro_after_init = {
0473     .input_min = 2000000,
0474     .input_max = 40000000,
0475     .cf_min = 1000000,
0476     .cf_max = 6000000,
0477     .vco_min = 48000000,
0478     .vco_max = 960000000,
0479     .base_reg = PLLU_BASE,
0480     .misc_reg = PLLU_MISC,
0481     .lock_mask = PLL_BASE_LOCK,
0482     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0483     .lock_delay = 1000,
0484     .pdiv_tohw = pllu_p,
0485     .freq_table = pll_u_freq_table,
0486     .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0487          TEGRA_PLL_HAS_LOCK_ENABLE,
0488 };
0489 
0490 static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
0491     .input_min = 2000000,
0492     .input_max = 31000000,
0493     .cf_min = 1000000,
0494     .cf_max = 6000000,
0495     .vco_min = 20000000,
0496     .vco_max = 1700000000,
0497     .base_reg = PLLX_BASE,
0498     .misc_reg = PLLX_MISC,
0499     .lock_mask = PLL_BASE_LOCK,
0500     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0501     .lock_delay = 300,
0502     .freq_table = pll_x_freq_table,
0503     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
0504          TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0505     .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
0506     .post_rate_change = tegra_cclk_post_pllx_rate_change,
0507 };
0508 
0509 static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
0510     .input_min = 12000000,
0511     .input_max = 216000000,
0512     .cf_min = 12000000,
0513     .cf_max = 12000000,
0514     .vco_min = 1200000000,
0515     .vco_max = 2400000000U,
0516     .base_reg = PLLE_BASE,
0517     .misc_reg = PLLE_MISC,
0518     .lock_mask = PLLE_MISC_LOCK,
0519     .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
0520     .lock_delay = 300,
0521     .pdiv_tohw = plle_p,
0522     .freq_table = pll_e_freq_table,
0523     .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
0524          TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
0525     .fixed_rate = 100000000,
0526 };
0527 
0528 static unsigned long tegra30_input_freq[] = {
0529     [ 0] = 13000000,
0530     [ 1] = 16800000,
0531     [ 4] = 19200000,
0532     [ 5] = 38400000,
0533     [ 8] = 12000000,
0534     [ 9] = 48000000,
0535     [12] = 26000000,
0536 };
0537 
0538 static struct tegra_devclk devclks[] = {
0539     { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
0540     { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
0541     { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
0542     { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
0543     { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
0544     { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
0545     { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
0546     { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
0547     { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
0548     { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
0549     { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
0550     { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
0551     { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
0552     { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
0553     { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
0554     { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
0555     { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
0556     { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
0557     { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
0558     { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
0559     { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
0560     { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
0561     { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
0562     { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
0563     { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
0564     { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
0565     { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
0566     { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
0567     { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
0568     { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
0569     { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
0570     { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
0571     { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
0572     { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
0573     { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
0574     { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
0575     { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
0576     { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
0577     { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
0578     { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
0579     { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
0580     { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
0581     { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
0582     { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
0583     { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
0584     { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
0585     { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
0586     { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
0587     { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
0588     { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
0589     { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
0590     { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
0591     { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
0592     { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
0593     { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
0594     { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
0595     { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
0596     { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
0597     { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
0598     { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
0599     { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
0600     { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
0601     { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
0602     { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
0603     { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
0604     { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
0605     { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
0606     { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
0607     { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
0608     { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
0609     { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
0610     { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
0611     { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
0612     { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
0613     { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
0614     { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
0615     { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
0616     { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
0617     { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
0618     { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
0619     { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
0620     { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
0621     { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
0622     { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
0623     { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
0624     { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
0625     { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
0626     { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
0627     { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
0628     { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
0629     { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
0630     { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
0631     { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
0632     { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
0633     { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
0634     { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
0635     { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
0636     { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
0637     { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
0638     { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
0639     { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
0640     { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
0641     { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
0642     { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
0643     { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
0644     { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
0645     { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
0646     { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
0647     { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
0648     { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
0649     { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
0650     { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
0651     { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
0652     { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
0653     { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
0654     { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
0655     { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
0656     { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
0657     { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
0658     { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
0659     { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
0660     { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
0661     { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
0662     { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
0663     { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
0664     { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
0665     { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
0666     { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
0667     { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
0668     { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
0669     { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
0670     { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
0671     { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
0672     { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
0673     { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
0674     { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
0675     { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
0676     { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
0677     { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
0678     { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
0679     { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
0680     { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
0681     { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
0682     { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
0683     { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
0684     { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
0685     { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
0686 };
0687 
0688 static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
0689     [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
0690     [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
0691     [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
0692     [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
0693     [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
0694     [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
0695     [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
0696     [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
0697     [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
0698     [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
0699     [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
0700     [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
0701     [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
0702     [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
0703     [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
0704     [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
0705     [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
0706     [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
0707     [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
0708     [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
0709     [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
0710     [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
0711     [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
0712     [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
0713     [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
0714     [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
0715     [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
0716     [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
0717     [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
0718     [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
0719     [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
0720     [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
0721     [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
0722     [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
0723     [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
0724     [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
0725     [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
0726     [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
0727     [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
0728     [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
0729     [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
0730     [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
0731     [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
0732     [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
0733     [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
0734     [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
0735     [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
0736     [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
0737     [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
0738     [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
0739     [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
0740     [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
0741     [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
0742     [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
0743     [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
0744     [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
0745     [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
0746     [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
0747     [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
0748     [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
0749     [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
0750     [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
0751     [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
0752     [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
0753     [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
0754     [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
0755     [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
0756     [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
0757     [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
0758     [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
0759     [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
0760     [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
0761     [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
0762     [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
0763     [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
0764     [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
0765     [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
0766     [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
0767     [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
0768     [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
0769     [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
0770     [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
0771     [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
0772     [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
0773     [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
0774     [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
0775     [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
0776     [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
0777     [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
0778     [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
0779     [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
0780     [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
0781     [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
0782     [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
0783     [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
0784     [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
0785     [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
0786     [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
0787     [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
0788     [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
0789     [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
0790     [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
0791     [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
0792     [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
0793     [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
0794     [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
0795     [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
0796     [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
0797     [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
0798     [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
0799     [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
0800     [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
0801     [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
0802     [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
0803     [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
0804     [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
0805     [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
0806     [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
0807     [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
0808     [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
0809     [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },
0810 };
0811 
0812 static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
0813 
0814 static void __init tegra30_pll_init(void)
0815 {
0816     struct clk *clk;
0817 
0818     /* PLLC_OUT1 */
0819     clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
0820                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0821                 8, 8, 1, NULL);
0822     clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
0823                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
0824                 0, NULL);
0825     clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
0826 
0827     /* PLLM_OUT1 */
0828     clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
0829                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0830                 8, 8, 1, NULL);
0831     clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
0832                 clk_base + PLLM_OUT, 1, 0,
0833                 CLK_SET_RATE_PARENT, 0, NULL);
0834     clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
0835 
0836     /* PLLX */
0837     clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
0838                 &pll_x_params, NULL);
0839     clks[TEGRA30_CLK_PLL_X] = clk;
0840 
0841     /* PLLX_OUT0 */
0842     clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
0843                     CLK_SET_RATE_PARENT, 1, 2);
0844     clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
0845 
0846     /* PLLU */
0847     clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,
0848                       &pll_u_params, NULL);
0849     clks[TEGRA30_CLK_PLL_U] = clk;
0850 
0851     /* PLLD */
0852     clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
0853                 &pll_d_params, &pll_d_lock);
0854     clks[TEGRA30_CLK_PLL_D] = clk;
0855 
0856     /* PLLD_OUT0 */
0857     clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
0858                     CLK_SET_RATE_PARENT, 1, 2);
0859     clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
0860 
0861     /* PLLD2 */
0862     clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
0863                 &pll_d2_params, NULL);
0864     clks[TEGRA30_CLK_PLL_D2] = clk;
0865 
0866     /* PLLD2_OUT0 */
0867     clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
0868                     CLK_SET_RATE_PARENT, 1, 2);
0869     clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
0870 
0871     /* PLLE */
0872     clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
0873                    ARRAY_SIZE(pll_e_parents),
0874                    CLK_SET_RATE_NO_REPARENT,
0875                    clk_base + PLLE_AUX, 2, 1, 0, NULL);
0876 }
0877 
0878 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
0879                     "pll_p_cclkg", "pll_p_out4_cclkg",
0880                     "pll_p_out3_cclkg", "unused", "pll_x" };
0881 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
0882                      "pll_p_cclklp", "pll_p_out4_cclklp",
0883                      "pll_p_out3_cclklp", "unused", "pll_x",
0884                      "pll_x_out0" };
0885 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
0886                       "pll_p_out3", "pll_p_out2", "unused",
0887                       "clk_32k", "pll_m_out1" };
0888 
0889 static void __init tegra30_super_clk_init(void)
0890 {
0891     struct clk *clk;
0892 
0893     /*
0894      * Clock input to cclk_g divided from pll_p using
0895      * U71 divider of cclk_g.
0896      */
0897     clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
0898                 clk_base + SUPER_CCLKG_DIVIDER, 0,
0899                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
0900     clk_register_clkdev(clk, "pll_p_cclkg", NULL);
0901 
0902     /*
0903      * Clock input to cclk_g divided from pll_p_out3 using
0904      * U71 divider of cclk_g.
0905      */
0906     clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
0907                 clk_base + SUPER_CCLKG_DIVIDER, 0,
0908                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
0909     clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
0910 
0911     /*
0912      * Clock input to cclk_g divided from pll_p_out4 using
0913      * U71 divider of cclk_g.
0914      */
0915     clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
0916                 clk_base + SUPER_CCLKG_DIVIDER, 0,
0917                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
0918     clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
0919 
0920     /* CCLKG */
0921     clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
0922                   ARRAY_SIZE(cclk_g_parents),
0923                   CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
0924                   clk_base + CCLKG_BURST_POLICY,
0925                   0, NULL);
0926     clks[TEGRA30_CLK_CCLK_G] = clk;
0927 
0928     /*
0929      * Clock input to cclk_lp divided from pll_p using
0930      * U71 divider of cclk_lp.
0931      */
0932     clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
0933                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
0934                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
0935     clk_register_clkdev(clk, "pll_p_cclklp", NULL);
0936 
0937     /*
0938      * Clock input to cclk_lp divided from pll_p_out3 using
0939      * U71 divider of cclk_lp.
0940      */
0941     clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
0942                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
0943                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
0944     clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
0945 
0946     /*
0947      * Clock input to cclk_lp divided from pll_p_out4 using
0948      * U71 divider of cclk_lp.
0949      */
0950     clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
0951                 clk_base + SUPER_CCLKLP_DIVIDER, 0,
0952                 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
0953     clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
0954 
0955     /* CCLKLP */
0956     clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
0957                   ARRAY_SIZE(cclk_lp_parents),
0958                   CLK_SET_RATE_PARENT,
0959                   clk_base + CCLKLP_BURST_POLICY,
0960                   TEGRA_DIVIDER_2, 4, 8, 9,
0961                   NULL);
0962     clks[TEGRA30_CLK_CCLK_LP] = clk;
0963 
0964     /* twd */
0965     clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
0966                     CLK_SET_RATE_PARENT, 1, 2);
0967     clks[TEGRA30_CLK_TWD] = clk;
0968 
0969     tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
0970 }
0971 
0972 static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
0973                      "clk_m" };
0974 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
0975 static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
0976                        "clk_m" };
0977 static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
0978 static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
0979                          "pll_a_out0", "pll_c",
0980                          "pll_d2_out0", "clk_m" };
0981 static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
0982                           "pll_d2_out0" };
0983 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
0984 
0985 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
0986     TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
0987     TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
0988     TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
0989     TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
0990     TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
0991     TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2),
0992     TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
0993     TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
0994     TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
0995 };
0996 
0997 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
0998     TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
0999 };
1000 
1001 static void __init tegra30_periph_clk_init(void)
1002 {
1003     struct tegra_periph_init_data *data;
1004     struct clk *clk;
1005     unsigned int i;
1006 
1007     /* dsia */
1008     clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1009                     0, 48, periph_clk_enb_refcnt);
1010     clks[TEGRA30_CLK_DSIA] = clk;
1011 
1012     /* pcie */
1013     clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1014                     70, periph_clk_enb_refcnt);
1015     clks[TEGRA30_CLK_PCIE] = clk;
1016 
1017     /* afi */
1018     clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1019                     periph_clk_enb_refcnt);
1020     clks[TEGRA30_CLK_AFI] = clk;
1021 
1022     /* emc */
1023     clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);
1024 
1025     clks[TEGRA30_CLK_EMC] = clk;
1026 
1027     clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1028                     NULL);
1029     clks[TEGRA30_CLK_MC] = clk;
1030 
1031     /* cml0 */
1032     clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1033                 0, 0, &cml_lock);
1034     clks[TEGRA30_CLK_CML0] = clk;
1035 
1036     /* cml1 */
1037     clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1038                 1, 0, &cml_lock);
1039     clks[TEGRA30_CLK_CML1] = clk;
1040 
1041     for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1042         data = &tegra_periph_clk_list[i];
1043         clk = tegra_clk_register_periph_data(clk_base, data);
1044         clks[data->clk_id] = clk;
1045     }
1046 
1047     for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1048         data = &tegra_periph_nodiv_clk_list[i];
1049         clk = tegra_clk_register_periph_nodiv(data->name,
1050                     data->p.parent_names,
1051                     data->num_parents, &data->periph,
1052                     clk_base, data->offset);
1053         clks[data->clk_id] = clk;
1054     }
1055 
1056     tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1057 }
1058 
1059 /* Tegra30 CPU clock and reset control functions */
1060 static void tegra30_wait_cpu_in_reset(u32 cpu)
1061 {
1062     unsigned int reg;
1063 
1064     do {
1065         reg = readl(clk_base +
1066                 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1067         cpu_relax();
1068     } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1069 
1070     return;
1071 }
1072 
1073 static void tegra30_put_cpu_in_reset(u32 cpu)
1074 {
1075     writel(CPU_RESET(cpu),
1076            clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1077     dmb();
1078 }
1079 
1080 static void tegra30_cpu_out_of_reset(u32 cpu)
1081 {
1082     writel(CPU_RESET(cpu),
1083            clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1084     wmb();
1085 }
1086 
1087 static void tegra30_enable_cpu_clock(u32 cpu)
1088 {
1089     writel(CPU_CLOCK(cpu),
1090            clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1091     readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1092 }
1093 
1094 static void tegra30_disable_cpu_clock(u32 cpu)
1095 {
1096     unsigned int reg;
1097 
1098     reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1099     writel(reg | CPU_CLOCK(cpu),
1100            clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1101 }
1102 
1103 #ifdef CONFIG_PM_SLEEP
1104 static bool tegra30_cpu_rail_off_ready(void)
1105 {
1106     unsigned int cpu_rst_status;
1107     int cpu_pwr_status;
1108 
1109     cpu_rst_status = readl(clk_base +
1110                 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1111     cpu_pwr_status = tegra_pmc_cpu_is_powered(1) ||
1112              tegra_pmc_cpu_is_powered(2) ||
1113              tegra_pmc_cpu_is_powered(3);
1114 
1115     if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1116         return false;
1117 
1118     return true;
1119 }
1120 
1121 static void tegra30_cpu_clock_suspend(void)
1122 {
1123     /* switch coresite to clk_m, save off original source */
1124     tegra30_cpu_clk_sctx.clk_csite_src =
1125                 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1126     writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
1127 
1128     tegra30_cpu_clk_sctx.cpu_burst =
1129                 readl(clk_base + CLK_RESET_CCLK_BURST);
1130     tegra30_cpu_clk_sctx.pllx_base =
1131                 readl(clk_base + CLK_RESET_PLLX_BASE);
1132     tegra30_cpu_clk_sctx.pllx_misc =
1133                 readl(clk_base + CLK_RESET_PLLX_MISC);
1134     tegra30_cpu_clk_sctx.cclk_divider =
1135                 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1136 }
1137 
1138 static void tegra30_cpu_clock_resume(void)
1139 {
1140     unsigned int reg, policy;
1141     u32 misc, base;
1142 
1143     /* Is CPU complex already running on PLLX? */
1144     reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1145     policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1146 
1147     if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1148         reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1149     else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1150         reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1151     else
1152         BUG();
1153 
1154     if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1155         misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);
1156         base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);
1157 
1158         if (misc != tegra30_cpu_clk_sctx.pllx_misc ||
1159             base != tegra30_cpu_clk_sctx.pllx_base) {
1160             /* restore PLLX settings if CPU is on different PLL */
1161             writel(tegra30_cpu_clk_sctx.pllx_misc,
1162                         clk_base + CLK_RESET_PLLX_MISC);
1163             writel(tegra30_cpu_clk_sctx.pllx_base,
1164                         clk_base + CLK_RESET_PLLX_BASE);
1165 
1166             /* wait for PLL stabilization if PLLX was enabled */
1167             if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1168                 udelay(300);
1169         }
1170     }
1171 
1172     /*
1173      * Restore original burst policy setting for calls resulting from CPU
1174      * LP2 in idle or system suspend.
1175      */
1176     writel(tegra30_cpu_clk_sctx.cclk_divider,
1177                     clk_base + CLK_RESET_CCLK_DIVIDER);
1178     writel(tegra30_cpu_clk_sctx.cpu_burst,
1179                     clk_base + CLK_RESET_CCLK_BURST);
1180 
1181     writel(tegra30_cpu_clk_sctx.clk_csite_src,
1182                     clk_base + CLK_RESET_SOURCE_CSITE);
1183 }
1184 #endif
1185 
1186 static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1187     .wait_for_reset = tegra30_wait_cpu_in_reset,
1188     .put_in_reset   = tegra30_put_cpu_in_reset,
1189     .out_of_reset   = tegra30_cpu_out_of_reset,
1190     .enable_clock   = tegra30_enable_cpu_clock,
1191     .disable_clock  = tegra30_disable_cpu_clock,
1192 #ifdef CONFIG_PM_SLEEP
1193     .rail_off_ready = tegra30_cpu_rail_off_ready,
1194     .suspend    = tegra30_cpu_clock_suspend,
1195     .resume     = tegra30_cpu_clock_resume,
1196 #endif
1197 };
1198 
1199 static struct tegra_clk_init_table init_table[] = {
1200     { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1201     { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1202     { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1203     { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1204     { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1205     { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 0 },
1206     { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
1207     { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1208     { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1209     { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1210     { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1211     { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1212     { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1213     { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1214     { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1215     { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
1216     { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
1217     { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1218     { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1219     { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1220     { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1221     { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1222     { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1223     { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
1224     { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
1225     { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1226     { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1227     { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1228     { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1229     { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
1230     { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },
1231     { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1232     { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1233     { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1234     { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1235     { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1236     { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1237     { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1238     { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
1239     { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
1240     /* must be the last entry */
1241     { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1242 };
1243 
1244 /*
1245  * Some clocks may be used by different drivers depending on the board
1246  * configuration.  List those here to register them twice in the clock lookup
1247  * table under two names.
1248  */
1249 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1250     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1251     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1252     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1253     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1254     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1255     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1256     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1257     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1258     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1259     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1260     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1261     /* must be the last entry */
1262     TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
1263 };
1264 
1265 static const struct of_device_id pmc_match[] __initconst = {
1266     { .compatible = "nvidia,tegra30-pmc" },
1267     { },
1268 };
1269 
1270 static struct tegra_audio_clk_info tegra30_audio_plls[] = {
1271     { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1272 };
1273 
1274 static bool tegra30_car_initialized;
1275 
1276 static struct clk *tegra30_clk_src_onecell_get(struct of_phandle_args *clkspec,
1277                            void *data)
1278 {
1279     struct clk_hw *hw;
1280     struct clk *clk;
1281 
1282     /*
1283      * Timer clocks are needed early, the rest of the clocks shouldn't be
1284      * available to device drivers until clock tree is fully initialized.
1285      */
1286     if (clkspec->args[0] != TEGRA30_CLK_RTC &&
1287         clkspec->args[0] != TEGRA30_CLK_TWD &&
1288         clkspec->args[0] != TEGRA30_CLK_TIMER &&
1289         !tegra30_car_initialized)
1290         return ERR_PTR(-EPROBE_DEFER);
1291 
1292     clk = of_clk_src_onecell_get(clkspec, data);
1293     if (IS_ERR(clk))
1294         return clk;
1295 
1296     hw = __clk_get_hw(clk);
1297 
1298     if (clkspec->args[0] == TEGRA30_CLK_EMC) {
1299         if (!tegra20_clk_emc_driver_available(hw))
1300             return ERR_PTR(-EPROBE_DEFER);
1301     }
1302 
1303     return clk;
1304 }
1305 
1306 static void __init tegra30_clock_init(struct device_node *np)
1307 {
1308     struct device_node *node;
1309 
1310     clk_base = of_iomap(np, 0);
1311     if (!clk_base) {
1312         pr_err("ioremap tegra30 CAR failed\n");
1313         return;
1314     }
1315 
1316     node = of_find_matching_node(NULL, pmc_match);
1317     if (!node) {
1318         pr_err("Failed to find pmc node\n");
1319         BUG();
1320     }
1321 
1322     pmc_base = of_iomap(node, 0);
1323     if (!pmc_base) {
1324         pr_err("Can't map pmc registers\n");
1325         BUG();
1326     }
1327 
1328     clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1329                 TEGRA30_CLK_PERIPH_BANKS);
1330     if (!clks)
1331         return;
1332 
1333     if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1334                    ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
1335                    NULL) < 0)
1336         return;
1337 
1338     tegra_fixed_clk_init(tegra30_clks);
1339     tegra30_pll_init();
1340     tegra30_super_clk_init();
1341     tegra30_periph_clk_init();
1342     tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1343                  tegra30_audio_plls,
1344                  ARRAY_SIZE(tegra30_audio_plls), 24000000);
1345 
1346     tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1347 
1348     tegra_add_of_provider(np, tegra30_clk_src_onecell_get);
1349 
1350     tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1351 }
1352 CLK_OF_DECLARE_DRIVER(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1353 
1354 /*
1355  * Clocks that use runtime PM can't be created at the tegra30_clock_init
1356  * time because drivers' base isn't initialized yet, and thus platform
1357  * devices can't be created for the clocks.  Hence we need to split the
1358  * registration of the clocks into two phases.  The first phase registers
1359  * essential clocks which don't require RPM and are actually used during
1360  * early boot.  The second phase registers clocks which use RPM and this
1361  * is done when device drivers' core API is ready.
1362  */
1363 static int tegra30_car_probe(struct platform_device *pdev)
1364 {
1365     struct clk *clk;
1366 
1367     /* PLLC */
1368     clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
1369                      &pll_c_params, NULL);
1370     clks[TEGRA30_CLK_PLL_C] = clk;
1371 
1372     /* PLLE */
1373     clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1374                       CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1375     clks[TEGRA30_CLK_PLL_E] = clk;
1376 
1377     /* PLLM */
1378     clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
1379                      CLK_SET_RATE_GATE, &pll_m_params, NULL);
1380     clks[TEGRA30_CLK_PLL_M] = clk;
1381 
1382     /* SCLK */
1383     clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1384                        ARRAY_SIZE(sclk_parents),
1385                        CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1386                        clk_base + SCLK_BURST_POLICY,
1387                        0, 4, 0, 0, NULL);
1388     clks[TEGRA30_CLK_SCLK] = clk;
1389 
1390     tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1391     tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1392     tegra30_car_initialized = true;
1393 
1394     return 0;
1395 }
1396 
1397 static const struct of_device_id tegra30_car_match[] = {
1398     { .compatible = "nvidia,tegra30-car" },
1399     { }
1400 };
1401 
1402 static struct platform_driver tegra30_car_driver = {
1403     .driver = {
1404         .name = "tegra30-car",
1405         .of_match_table = tegra30_car_match,
1406         .suppress_bind_attrs = true,
1407     },
1408     .probe = tegra30_car_probe,
1409 };
1410 
1411 /*
1412  * Clock driver must be registered before memory controller driver,
1413  * which doesn't support deferred probing for today and is registered
1414  * from arch init-level.
1415  */
1416 static int tegra30_car_init(void)
1417 {
1418     return platform_driver_register(&tegra30_car_driver);
1419 }
1420 postcore_initcall(tegra30_car_init);
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