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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/io.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/clkdev.h>
0009 #include <linux/init.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/clk/tegra.h>
0015 #include <linux/delay.h>
0016 #include <dt-bindings/clock/tegra20-car.h>
0017 
0018 #include "clk.h"
0019 #include "clk-id.h"
0020 
0021 #define MISC_CLK_ENB 0x48
0022 
0023 #define OSC_CTRL 0x50
0024 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
0025 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
0026 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
0027 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
0028 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
0029 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
0030 
0031 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
0032 #define OSC_CTRL_PLL_REF_DIV_1      (0<<28)
0033 #define OSC_CTRL_PLL_REF_DIV_2      (1<<28)
0034 #define OSC_CTRL_PLL_REF_DIV_4      (2<<28)
0035 
0036 #define OSC_FREQ_DET 0x58
0037 #define OSC_FREQ_DET_TRIG (1<<31)
0038 
0039 #define OSC_FREQ_DET_STATUS 0x5c
0040 #define OSC_FREQ_DET_BUSY (1<<31)
0041 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
0042 
0043 #define TEGRA20_CLK_PERIPH_BANKS    3
0044 
0045 #define PLLS_BASE 0xf0
0046 #define PLLS_MISC 0xf4
0047 #define PLLC_BASE 0x80
0048 #define PLLC_MISC 0x8c
0049 #define PLLM_BASE 0x90
0050 #define PLLM_MISC 0x9c
0051 #define PLLP_BASE 0xa0
0052 #define PLLP_MISC 0xac
0053 #define PLLA_BASE 0xb0
0054 #define PLLA_MISC 0xbc
0055 #define PLLU_BASE 0xc0
0056 #define PLLU_MISC 0xcc
0057 #define PLLD_BASE 0xd0
0058 #define PLLD_MISC 0xdc
0059 #define PLLX_BASE 0xe0
0060 #define PLLX_MISC 0xe4
0061 #define PLLE_BASE 0xe8
0062 #define PLLE_MISC 0xec
0063 
0064 #define PLL_BASE_LOCK BIT(27)
0065 #define PLLE_MISC_LOCK BIT(11)
0066 
0067 #define PLL_MISC_LOCK_ENABLE 18
0068 #define PLLDU_MISC_LOCK_ENABLE 22
0069 #define PLLE_MISC_LOCK_ENABLE 9
0070 
0071 #define PLLC_OUT 0x84
0072 #define PLLM_OUT 0x94
0073 #define PLLP_OUTA 0xa4
0074 #define PLLP_OUTB 0xa8
0075 #define PLLA_OUT 0xb4
0076 
0077 #define CCLK_BURST_POLICY 0x20
0078 #define SUPER_CCLK_DIVIDER 0x24
0079 #define SCLK_BURST_POLICY 0x28
0080 #define SUPER_SCLK_DIVIDER 0x2c
0081 #define CLK_SYSTEM_RATE 0x30
0082 
0083 #define CCLK_BURST_POLICY_SHIFT 28
0084 #define CCLK_RUN_POLICY_SHIFT   4
0085 #define CCLK_IDLE_POLICY_SHIFT  0
0086 #define CCLK_IDLE_POLICY    1
0087 #define CCLK_RUN_POLICY     2
0088 #define CCLK_BURST_POLICY_PLLX  8
0089 
0090 #define CLK_SOURCE_I2S1 0x100
0091 #define CLK_SOURCE_I2S2 0x104
0092 #define CLK_SOURCE_PWM 0x110
0093 #define CLK_SOURCE_SPI 0x114
0094 #define CLK_SOURCE_XIO 0x120
0095 #define CLK_SOURCE_TWC 0x12c
0096 #define CLK_SOURCE_IDE 0x144
0097 #define CLK_SOURCE_HDMI 0x18c
0098 #define CLK_SOURCE_DISP1 0x138
0099 #define CLK_SOURCE_DISP2 0x13c
0100 #define CLK_SOURCE_CSITE 0x1d4
0101 #define CLK_SOURCE_I2C1 0x124
0102 #define CLK_SOURCE_I2C2 0x198
0103 #define CLK_SOURCE_I2C3 0x1b8
0104 #define CLK_SOURCE_DVC 0x128
0105 #define CLK_SOURCE_UARTA 0x178
0106 #define CLK_SOURCE_UARTB 0x17c
0107 #define CLK_SOURCE_UARTC 0x1a0
0108 #define CLK_SOURCE_UARTD 0x1c0
0109 #define CLK_SOURCE_UARTE 0x1c4
0110 #define CLK_SOURCE_EMC 0x19c
0111 
0112 #define AUDIO_SYNC_CLK 0x38
0113 
0114 /* Tegra CPU clock and reset control regs */
0115 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX      0x4c
0116 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET  0x340
0117 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR  0x344
0118 
0119 #define CPU_CLOCK(cpu)  (0x1 << (8 + cpu))
0120 #define CPU_RESET(cpu)  (0x1111ul << (cpu))
0121 
0122 #ifdef CONFIG_PM_SLEEP
0123 static struct cpu_clk_suspend_context {
0124     u32 pllx_misc;
0125     u32 pllx_base;
0126 
0127     u32 cpu_burst;
0128     u32 clk_csite_src;
0129     u32 cclk_divider;
0130 } tegra20_cpu_clk_sctx;
0131 #endif
0132 
0133 static void __iomem *clk_base;
0134 static void __iomem *pmc_base;
0135 
0136 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,   \
0137                 _clk_num, _gate_flags, _clk_id) \
0138     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0139             30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,  \
0140             _clk_num, \
0141             _gate_flags, _clk_id)
0142 
0143 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
0144                   _clk_num, _gate_flags, _clk_id)   \
0145     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0146             30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
0147             _clk_num, _gate_flags,  \
0148             _clk_id)
0149 
0150 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
0151                   _mux_shift, _mux_width, _clk_num, \
0152                   _gate_flags, _clk_id)         \
0153     TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,   \
0154             _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
0155             _clk_num, _gate_flags,  \
0156             _clk_id)
0157 
0158 static struct clk **clks;
0159 
0160 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
0161     { 12000000, 600000000, 600, 12, 1, 8 },
0162     { 13000000, 600000000, 600, 13, 1, 8 },
0163     { 19200000, 600000000, 500, 16, 1, 6 },
0164     { 26000000, 600000000, 600, 26, 1, 8 },
0165     {        0,         0,   0,  0, 0, 0 },
0166 };
0167 
0168 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
0169     { 12000000, 666000000, 666, 12, 1, 8 },
0170     { 13000000, 666000000, 666, 13, 1, 8 },
0171     { 19200000, 666000000, 555, 16, 1, 8 },
0172     { 26000000, 666000000, 666, 26, 1, 8 },
0173     { 12000000, 600000000, 600, 12, 1, 8 },
0174     { 13000000, 600000000, 600, 13, 1, 8 },
0175     { 19200000, 600000000, 375, 12, 1, 6 },
0176     { 26000000, 600000000, 600, 26, 1, 8 },
0177     {        0,         0,   0,  0, 0, 0 },
0178 };
0179 
0180 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
0181     { 12000000, 216000000, 432, 12, 2, 8 },
0182     { 13000000, 216000000, 432, 13, 2, 8 },
0183     { 19200000, 216000000,  90,  4, 2, 1 },
0184     { 26000000, 216000000, 432, 26, 2, 8 },
0185     { 12000000, 432000000, 432, 12, 1, 8 },
0186     { 13000000, 432000000, 432, 13, 1, 8 },
0187     { 19200000, 432000000,  90,  4, 1, 1 },
0188     { 26000000, 432000000, 432, 26, 1, 8 },
0189     {        0,         0,   0,  0, 0, 0 },
0190 };
0191 
0192 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
0193     { 28800000, 56448000, 49, 25, 1, 1 },
0194     { 28800000, 73728000, 64, 25, 1, 1 },
0195     { 28800000, 24000000,  5,  6, 1, 1 },
0196     {        0,        0,  0,  0, 0, 0 },
0197 };
0198 
0199 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
0200     { 12000000,  216000000,  216, 12, 1,  4 },
0201     { 13000000,  216000000,  216, 13, 1,  4 },
0202     { 19200000,  216000000,  135, 12, 1,  3 },
0203     { 26000000,  216000000,  216, 26, 1,  4 },
0204     { 12000000,  594000000,  594, 12, 1,  8 },
0205     { 13000000,  594000000,  594, 13, 1,  8 },
0206     { 19200000,  594000000,  495, 16, 1,  8 },
0207     { 26000000,  594000000,  594, 26, 1,  8 },
0208     { 12000000, 1000000000, 1000, 12, 1, 12 },
0209     { 13000000, 1000000000, 1000, 13, 1, 12 },
0210     { 19200000, 1000000000,  625, 12, 1,  8 },
0211     { 26000000, 1000000000, 1000, 26, 1, 12 },
0212     {        0,          0,    0,  0, 0,  0 },
0213 };
0214 
0215 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
0216     { 12000000, 480000000, 960, 12, 1, 0 },
0217     { 13000000, 480000000, 960, 13, 1, 0 },
0218     { 19200000, 480000000, 200,  4, 1, 0 },
0219     { 26000000, 480000000, 960, 26, 1, 0 },
0220     {        0,         0,   0,  0, 0, 0 },
0221 };
0222 
0223 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
0224     /* 1 GHz */
0225     { 12000000, 1000000000, 1000, 12, 1, 12 },
0226     { 13000000, 1000000000, 1000, 13, 1, 12 },
0227     { 19200000, 1000000000,  625, 12, 1,  8 },
0228     { 26000000, 1000000000, 1000, 26, 1, 12 },
0229     /* 912 MHz */
0230     { 12000000,  912000000,  912, 12, 1, 12 },
0231     { 13000000,  912000000,  912, 13, 1, 12 },
0232     { 19200000,  912000000,  760, 16, 1,  8 },
0233     { 26000000,  912000000,  912, 26, 1, 12 },
0234     /* 816 MHz */
0235     { 12000000,  816000000,  816, 12, 1, 12 },
0236     { 13000000,  816000000,  816, 13, 1, 12 },
0237     { 19200000,  816000000,  680, 16, 1,  8 },
0238     { 26000000,  816000000,  816, 26, 1, 12 },
0239     /* 760 MHz */
0240     { 12000000,  760000000,  760, 12, 1, 12 },
0241     { 13000000,  760000000,  760, 13, 1, 12 },
0242     { 19200000,  760000000,  950, 24, 1,  8 },
0243     { 26000000,  760000000,  760, 26, 1, 12 },
0244     /* 750 MHz */
0245     { 12000000,  750000000,  750, 12, 1, 12 },
0246     { 13000000,  750000000,  750, 13, 1, 12 },
0247     { 19200000,  750000000,  625, 16, 1,  8 },
0248     { 26000000,  750000000,  750, 26, 1, 12 },
0249     /* 608 MHz */
0250     { 12000000,  608000000,  608, 12, 1, 12 },
0251     { 13000000,  608000000,  608, 13, 1, 12 },
0252     { 19200000,  608000000,  380, 12, 1,  8 },
0253     { 26000000,  608000000,  608, 26, 1, 12 },
0254     /* 456 MHz */
0255     { 12000000,  456000000,  456, 12, 1, 12 },
0256     { 13000000,  456000000,  456, 13, 1, 12 },
0257     { 19200000,  456000000,  380, 16, 1,  8 },
0258     { 26000000,  456000000,  456, 26, 1, 12 },
0259     /* 312 MHz */
0260     { 12000000,  312000000,  312, 12, 1, 12 },
0261     { 13000000,  312000000,  312, 13, 1, 12 },
0262     { 19200000,  312000000,  260, 16, 1,  8 },
0263     { 26000000,  312000000,  312, 26, 1, 12 },
0264     {        0,          0,    0,  0, 0,  0 },
0265 };
0266 
0267 static const struct pdiv_map plle_p[] = {
0268     { .pdiv = 1, .hw_val = 1 },
0269     { .pdiv = 0, .hw_val = 0 },
0270 };
0271 
0272 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
0273     { 12000000, 100000000, 200, 24, 1, 0 },
0274     {        0,         0,   0,  0, 0, 0 },
0275 };
0276 
0277 /* PLL parameters */
0278 static struct tegra_clk_pll_params pll_c_params = {
0279     .input_min = 2000000,
0280     .input_max = 31000000,
0281     .cf_min = 1000000,
0282     .cf_max = 6000000,
0283     .vco_min = 20000000,
0284     .vco_max = 1400000000,
0285     .base_reg = PLLC_BASE,
0286     .misc_reg = PLLC_MISC,
0287     .lock_mask = PLL_BASE_LOCK,
0288     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0289     .lock_delay = 300,
0290     .freq_table = pll_c_freq_table,
0291     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
0292 };
0293 
0294 static struct tegra_clk_pll_params pll_m_params = {
0295     .input_min = 2000000,
0296     .input_max = 31000000,
0297     .cf_min = 1000000,
0298     .cf_max = 6000000,
0299     .vco_min = 20000000,
0300     .vco_max = 1200000000,
0301     .base_reg = PLLM_BASE,
0302     .misc_reg = PLLM_MISC,
0303     .lock_mask = PLL_BASE_LOCK,
0304     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0305     .lock_delay = 300,
0306     .freq_table = pll_m_freq_table,
0307     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
0308 };
0309 
0310 static struct tegra_clk_pll_params pll_p_params = {
0311     .input_min = 2000000,
0312     .input_max = 31000000,
0313     .cf_min = 1000000,
0314     .cf_max = 6000000,
0315     .vco_min = 20000000,
0316     .vco_max = 1400000000,
0317     .base_reg = PLLP_BASE,
0318     .misc_reg = PLLP_MISC,
0319     .lock_mask = PLL_BASE_LOCK,
0320     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0321     .lock_delay = 300,
0322     .freq_table = pll_p_freq_table,
0323     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
0324          TEGRA_PLL_HAS_LOCK_ENABLE,
0325     .fixed_rate =  216000000,
0326 };
0327 
0328 static struct tegra_clk_pll_params pll_a_params = {
0329     .input_min = 2000000,
0330     .input_max = 31000000,
0331     .cf_min = 1000000,
0332     .cf_max = 6000000,
0333     .vco_min = 20000000,
0334     .vco_max = 1400000000,
0335     .base_reg = PLLA_BASE,
0336     .misc_reg = PLLA_MISC,
0337     .lock_mask = PLL_BASE_LOCK,
0338     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0339     .lock_delay = 300,
0340     .freq_table = pll_a_freq_table,
0341     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
0342 };
0343 
0344 static struct tegra_clk_pll_params pll_d_params = {
0345     .input_min = 2000000,
0346     .input_max = 40000000,
0347     .cf_min = 1000000,
0348     .cf_max = 6000000,
0349     .vco_min = 40000000,
0350     .vco_max = 1000000000,
0351     .base_reg = PLLD_BASE,
0352     .misc_reg = PLLD_MISC,
0353     .lock_mask = PLL_BASE_LOCK,
0354     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0355     .lock_delay = 1000,
0356     .freq_table = pll_d_freq_table,
0357     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
0358 };
0359 
0360 static const struct pdiv_map pllu_p[] = {
0361     { .pdiv = 1, .hw_val = 1 },
0362     { .pdiv = 2, .hw_val = 0 },
0363     { .pdiv = 0, .hw_val = 0 },
0364 };
0365 
0366 static struct tegra_clk_pll_params pll_u_params = {
0367     .input_min = 2000000,
0368     .input_max = 40000000,
0369     .cf_min = 1000000,
0370     .cf_max = 6000000,
0371     .vco_min = 48000000,
0372     .vco_max = 960000000,
0373     .base_reg = PLLU_BASE,
0374     .misc_reg = PLLU_MISC,
0375     .lock_mask = PLL_BASE_LOCK,
0376     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0377     .lock_delay = 1000,
0378     .pdiv_tohw = pllu_p,
0379     .freq_table = pll_u_freq_table,
0380     .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
0381 };
0382 
0383 static struct tegra_clk_pll_params pll_x_params = {
0384     .input_min = 2000000,
0385     .input_max = 31000000,
0386     .cf_min = 1000000,
0387     .cf_max = 6000000,
0388     .vco_min = 20000000,
0389     .vco_max = 1200000000,
0390     .base_reg = PLLX_BASE,
0391     .misc_reg = PLLX_MISC,
0392     .lock_mask = PLL_BASE_LOCK,
0393     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0394     .lock_delay = 300,
0395     .freq_table = pll_x_freq_table,
0396     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
0397     .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
0398     .post_rate_change = tegra_cclk_post_pllx_rate_change,
0399 };
0400 
0401 static struct tegra_clk_pll_params pll_e_params = {
0402     .input_min = 12000000,
0403     .input_max = 12000000,
0404     .cf_min = 0,
0405     .cf_max = 0,
0406     .vco_min = 0,
0407     .vco_max = 0,
0408     .base_reg = PLLE_BASE,
0409     .misc_reg = PLLE_MISC,
0410     .lock_mask = PLLE_MISC_LOCK,
0411     .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
0412     .lock_delay = 0,
0413     .pdiv_tohw = plle_p,
0414     .freq_table = pll_e_freq_table,
0415     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
0416          TEGRA_PLL_HAS_LOCK_ENABLE,
0417     .fixed_rate = 100000000,
0418 };
0419 
0420 static struct tegra_devclk devclks[] = {
0421     { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
0422     { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
0423     { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
0424     { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
0425     { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
0426     { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
0427     { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
0428     { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
0429     { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
0430     { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
0431     { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
0432     { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
0433     { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
0434     { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
0435     { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
0436     { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
0437     { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
0438     { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
0439     { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
0440     { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
0441     { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
0442     { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
0443     { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
0444     { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
0445     { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
0446     { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
0447     { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
0448     { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
0449     { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
0450     { .con_id = "csus", .dev_id =  "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
0451     { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
0452     { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
0453     { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
0454     { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
0455     { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
0456     { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
0457     { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
0458     { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
0459     { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
0460     { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
0461     { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
0462     { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
0463     { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
0464     { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
0465     { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
0466     { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
0467     { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
0468     { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
0469     { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
0470     { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
0471     { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
0472     { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
0473     { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
0474     { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
0475     { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
0476     { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
0477     { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
0478     { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
0479     { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
0480     { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
0481     { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
0482     { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
0483     { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
0484     { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
0485     { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
0486     { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
0487     { .con_id = "vi", .dev_id =  "tegra_camera", .dt_id = TEGRA20_CLK_VI },
0488     { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
0489     { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
0490     { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
0491     { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
0492     { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
0493     { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
0494     { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
0495     { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
0496     { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
0497     { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
0498     { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
0499     { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
0500     { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
0501     { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
0502     { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
0503     { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
0504     { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
0505     { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
0506     { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
0507     { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
0508     { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
0509     { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
0510     { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
0511     { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
0512     { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
0513     { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
0514     { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
0515 };
0516 
0517 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
0518     [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
0519     [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },
0520     [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
0521     [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
0522     [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
0523     [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
0524     [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
0525     [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
0526     [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
0527     [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
0528     [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
0529     [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
0530     [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
0531     [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
0532     [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
0533     [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
0534     [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
0535     [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
0536     [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
0537     [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
0538     [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
0539     [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
0540     [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
0541     [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
0542     [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
0543     [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
0544     [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
0545     [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
0546     [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
0547     [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
0548     [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
0549     [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
0550     [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
0551     [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
0552     [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
0553     [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
0554     [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
0555     [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
0556     [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
0557     [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
0558     [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
0559     [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
0560     [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
0561     [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
0562     [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
0563     [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
0564     [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
0565     [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
0566     [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
0567     [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
0568     [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
0569     [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
0570     [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
0571 };
0572 
0573 static unsigned long tegra20_clk_measure_input_freq(void)
0574 {
0575     u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
0576     u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
0577     u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
0578     unsigned long input_freq;
0579 
0580     switch (auto_clk_control) {
0581     case OSC_CTRL_OSC_FREQ_12MHZ:
0582         BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
0583         input_freq = 12000000;
0584         break;
0585     case OSC_CTRL_OSC_FREQ_13MHZ:
0586         BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
0587         input_freq = 13000000;
0588         break;
0589     case OSC_CTRL_OSC_FREQ_19_2MHZ:
0590         BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
0591         input_freq = 19200000;
0592         break;
0593     case OSC_CTRL_OSC_FREQ_26MHZ:
0594         BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
0595         input_freq = 26000000;
0596         break;
0597     default:
0598         pr_err("Unexpected clock autodetect value %d",
0599                auto_clk_control);
0600         BUG();
0601         return 0;
0602     }
0603 
0604     return input_freq;
0605 }
0606 
0607 static unsigned int tegra20_get_pll_ref_div(void)
0608 {
0609     u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
0610         OSC_CTRL_PLL_REF_DIV_MASK;
0611 
0612     switch (pll_ref_div) {
0613     case OSC_CTRL_PLL_REF_DIV_1:
0614         return 1;
0615     case OSC_CTRL_PLL_REF_DIV_2:
0616         return 2;
0617     case OSC_CTRL_PLL_REF_DIV_4:
0618         return 4;
0619     default:
0620         pr_err("Invalid pll ref divider %d\n", pll_ref_div);
0621         BUG();
0622     }
0623     return 0;
0624 }
0625 
0626 static void tegra20_pll_init(void)
0627 {
0628     struct clk *clk;
0629 
0630     /* PLLC */
0631     clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
0632                 &pll_c_params, NULL);
0633     clks[TEGRA20_CLK_PLL_C] = clk;
0634 
0635     /* PLLC_OUT1 */
0636     clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
0637                 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0638                 8, 8, 1, NULL);
0639     clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
0640                 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
0641                 0, NULL);
0642     clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
0643 
0644     /* PLLM */
0645     clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
0646                 CLK_SET_RATE_GATE, &pll_m_params, NULL);
0647     clks[TEGRA20_CLK_PLL_M] = clk;
0648 
0649     /* PLLM_OUT1 */
0650     clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
0651                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0652                 8, 8, 1, NULL);
0653     clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
0654                 clk_base + PLLM_OUT, 1, 0,
0655                 CLK_SET_RATE_PARENT, 0, NULL);
0656     clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
0657 
0658     /* PLLX */
0659     clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
0660                 &pll_x_params, NULL);
0661     clks[TEGRA20_CLK_PLL_X] = clk;
0662 
0663     /* PLLU */
0664     clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
0665                 &pll_u_params, NULL);
0666     clks[TEGRA20_CLK_PLL_U] = clk;
0667 
0668     /* PLLD */
0669     clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
0670                 &pll_d_params, NULL);
0671     clks[TEGRA20_CLK_PLL_D] = clk;
0672 
0673     /* PLLD_OUT0 */
0674     clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
0675                     CLK_SET_RATE_PARENT, 1, 2);
0676     clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
0677 
0678     /* PLLA */
0679     clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
0680                 &pll_a_params, NULL);
0681     clks[TEGRA20_CLK_PLL_A] = clk;
0682 
0683     /* PLLA_OUT0 */
0684     clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
0685                 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0686                 8, 8, 1, NULL);
0687     clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
0688                 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
0689                 CLK_SET_RATE_PARENT, 0, NULL);
0690     clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
0691 
0692     /* PLLE */
0693     clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
0694                  0, &pll_e_params, NULL);
0695     clks[TEGRA20_CLK_PLL_E] = clk;
0696 }
0697 
0698 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
0699                       "pll_p", "pll_p_out4",
0700                       "pll_p_out3", "clk_d", "pll_x" };
0701 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
0702                       "pll_p_out3", "pll_p_out2", "clk_d",
0703                       "clk_32k", "pll_m_out1" };
0704 
0705 static void tegra20_super_clk_init(void)
0706 {
0707     struct clk *clk;
0708 
0709     /* CCLK */
0710     clk = tegra_clk_register_super_cclk("cclk", cclk_parents,
0711                   ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
0712                   clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,
0713                   NULL);
0714     clks[TEGRA20_CLK_CCLK] = clk;
0715 
0716     /* twd */
0717     clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
0718     clks[TEGRA20_CLK_TWD] = clk;
0719 }
0720 
0721 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
0722                        "pll_a_out0", "unused", "unused",
0723                        "unused" };
0724 
0725 static void __init tegra20_audio_clk_init(void)
0726 {
0727     struct clk *clk;
0728 
0729     /* audio */
0730     clk = clk_register_mux(NULL, "audio_mux", audio_parents,
0731                 ARRAY_SIZE(audio_parents),
0732                 CLK_SET_RATE_NO_REPARENT,
0733                 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
0734     clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
0735                 clk_base + AUDIO_SYNC_CLK, 4,
0736                 CLK_GATE_SET_TO_DISABLE, NULL);
0737     clks[TEGRA20_CLK_AUDIO] = clk;
0738 
0739     /* audio_2x */
0740     clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
0741                     CLK_SET_RATE_PARENT, 2, 1);
0742     clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
0743                     TEGRA_PERIPH_NO_RESET, clk_base,
0744                     CLK_SET_RATE_PARENT, 89,
0745                     periph_clk_enb_refcnt);
0746     clks[TEGRA20_CLK_AUDIO_2X] = clk;
0747 }
0748 
0749 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
0750                       "clk_m" };
0751 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
0752                       "clk_m" };
0753 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
0754                      "clk_32k" };
0755 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
0756 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
0757                      "clk_m" };
0758 
0759 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
0760     TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents,     CLK_SOURCE_I2S1,   11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
0761     TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents,     CLK_SOURCE_I2S2,   18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
0762     TEGRA_INIT_DATA_MUX("spi",   mux_pllpcm_clkm,   CLK_SOURCE_SPI,   43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
0763     TEGRA_INIT_DATA_MUX("xio",   mux_pllpcm_clkm,   CLK_SOURCE_XIO,   45, 0, TEGRA20_CLK_XIO),
0764     TEGRA_INIT_DATA_MUX("twc",   mux_pllpcm_clkm,   CLK_SOURCE_TWC,   16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
0765     TEGRA_INIT_DATA_MUX("ide",   mux_pllpcm_clkm,   CLK_SOURCE_XIO,   25, 0, TEGRA20_CLK_IDE),
0766     TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm,   CLK_SOURCE_DVC,   47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
0767     TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm,   CLK_SOURCE_I2C1,   12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
0768     TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm,   CLK_SOURCE_I2C2,   54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
0769     TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm,   CLK_SOURCE_I2C3,   67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
0770     TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm,   CLK_SOURCE_HDMI,   51, 0, TEGRA20_CLK_HDMI),
0771     TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents,     CLK_SOURCE_PWM,   28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
0772 };
0773 
0774 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
0775     TEGRA_INIT_DATA_NODIV("uarta",  mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6,   TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
0776     TEGRA_INIT_DATA_NODIV("uartb",  mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7,   TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
0777     TEGRA_INIT_DATA_NODIV("uartc",  mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
0778     TEGRA_INIT_DATA_NODIV("uartd",  mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
0779     TEGRA_INIT_DATA_NODIV("uarte",  mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66,  TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
0780     TEGRA_INIT_DATA_NODIV("disp1",  mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27,  0, TEGRA20_CLK_DISP1),
0781     TEGRA_INIT_DATA_NODIV("disp2",  mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26,  0, TEGRA20_CLK_DISP2),
0782 };
0783 
0784 static void __init tegra20_periph_clk_init(void)
0785 {
0786     struct tegra_periph_init_data *data;
0787     struct clk *clk;
0788     unsigned int i;
0789 
0790     /* ac97 */
0791     clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
0792                     TEGRA_PERIPH_ON_APB,
0793                     clk_base, 0, 3, periph_clk_enb_refcnt);
0794     clks[TEGRA20_CLK_AC97] = clk;
0795 
0796     /* emc */
0797     clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
0798 
0799     clks[TEGRA20_CLK_EMC] = clk;
0800 
0801     clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
0802                     NULL);
0803     clks[TEGRA20_CLK_MC] = clk;
0804 
0805     /* dsi */
0806     clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
0807                     48, periph_clk_enb_refcnt);
0808     clk_register_clkdev(clk, NULL, "dsi");
0809     clks[TEGRA20_CLK_DSI] = clk;
0810 
0811     /* pex */
0812     clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
0813                     periph_clk_enb_refcnt);
0814     clks[TEGRA20_CLK_PEX] = clk;
0815 
0816     /* dev1 OSC divider */
0817     clk_register_divider(NULL, "dev1_osc_div", "clk_m",
0818                  0, clk_base + MISC_CLK_ENB, 22, 2,
0819                  CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
0820                  NULL);
0821 
0822     /* dev2 OSC divider */
0823     clk_register_divider(NULL, "dev2_osc_div", "clk_m",
0824                  0, clk_base + MISC_CLK_ENB, 20, 2,
0825                  CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
0826                  NULL);
0827 
0828     /* cdev1 */
0829     clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
0830                     clk_base, 0, 94, periph_clk_enb_refcnt);
0831     clks[TEGRA20_CLK_CDEV1] = clk;
0832 
0833     /* cdev2 */
0834     clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
0835                     clk_base, 0, 93, periph_clk_enb_refcnt);
0836     clks[TEGRA20_CLK_CDEV2] = clk;
0837 
0838     for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
0839         data = &tegra_periph_clk_list[i];
0840         clk = tegra_clk_register_periph_data(clk_base, data);
0841         clks[data->clk_id] = clk;
0842     }
0843 
0844     for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
0845         data = &tegra_periph_nodiv_clk_list[i];
0846         clk = tegra_clk_register_periph_nodiv(data->name,
0847                     data->p.parent_names,
0848                     data->num_parents, &data->periph,
0849                     clk_base, data->offset);
0850         clks[data->clk_id] = clk;
0851     }
0852 
0853     tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
0854 }
0855 
0856 static void __init tegra20_osc_clk_init(void)
0857 {
0858     struct clk *clk;
0859     unsigned long input_freq;
0860     unsigned int pll_ref_div;
0861 
0862     input_freq = tegra20_clk_measure_input_freq();
0863 
0864     /* clk_m */
0865     clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,
0866                       input_freq);
0867     clks[TEGRA20_CLK_CLK_M] = clk;
0868 
0869     /* pll_ref */
0870     pll_ref_div = tegra20_get_pll_ref_div();
0871     clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
0872                     CLK_SET_RATE_PARENT, 1, pll_ref_div);
0873     clks[TEGRA20_CLK_PLL_REF] = clk;
0874 }
0875 
0876 /* Tegra20 CPU clock and reset control functions */
0877 static void tegra20_wait_cpu_in_reset(u32 cpu)
0878 {
0879     unsigned int reg;
0880 
0881     do {
0882         reg = readl(clk_base +
0883                 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
0884         cpu_relax();
0885     } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
0886 
0887     return;
0888 }
0889 
0890 static void tegra20_put_cpu_in_reset(u32 cpu)
0891 {
0892     writel(CPU_RESET(cpu),
0893            clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
0894     dmb();
0895 }
0896 
0897 static void tegra20_cpu_out_of_reset(u32 cpu)
0898 {
0899     writel(CPU_RESET(cpu),
0900            clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
0901     wmb();
0902 }
0903 
0904 static void tegra20_enable_cpu_clock(u32 cpu)
0905 {
0906     unsigned int reg;
0907 
0908     reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
0909     writel(reg & ~CPU_CLOCK(cpu),
0910            clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
0911     barrier();
0912     reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
0913 }
0914 
0915 static void tegra20_disable_cpu_clock(u32 cpu)
0916 {
0917     unsigned int reg;
0918 
0919     reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
0920     writel(reg | CPU_CLOCK(cpu),
0921            clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
0922 }
0923 
0924 #ifdef CONFIG_PM_SLEEP
0925 static bool tegra20_cpu_rail_off_ready(void)
0926 {
0927     unsigned int cpu_rst_status;
0928 
0929     cpu_rst_status = readl(clk_base +
0930                    TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
0931 
0932     return !!(cpu_rst_status & 0x2);
0933 }
0934 
0935 static void tegra20_cpu_clock_suspend(void)
0936 {
0937     /* switch coresite to clk_m, save off original source */
0938     tegra20_cpu_clk_sctx.clk_csite_src =
0939                 readl(clk_base + CLK_SOURCE_CSITE);
0940     writel(3<<30, clk_base + CLK_SOURCE_CSITE);
0941 
0942     tegra20_cpu_clk_sctx.cpu_burst =
0943                 readl(clk_base + CCLK_BURST_POLICY);
0944     tegra20_cpu_clk_sctx.pllx_base =
0945                 readl(clk_base + PLLX_BASE);
0946     tegra20_cpu_clk_sctx.pllx_misc =
0947                 readl(clk_base + PLLX_MISC);
0948     tegra20_cpu_clk_sctx.cclk_divider =
0949                 readl(clk_base + SUPER_CCLK_DIVIDER);
0950 }
0951 
0952 static void tegra20_cpu_clock_resume(void)
0953 {
0954     unsigned int reg, policy;
0955     u32 misc, base;
0956 
0957     /* Is CPU complex already running on PLLX? */
0958     reg = readl(clk_base + CCLK_BURST_POLICY);
0959     policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
0960 
0961     if (policy == CCLK_IDLE_POLICY)
0962         reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
0963     else if (policy == CCLK_RUN_POLICY)
0964         reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
0965     else
0966         BUG();
0967 
0968     if (reg != CCLK_BURST_POLICY_PLLX) {
0969         misc = readl_relaxed(clk_base + PLLX_MISC);
0970         base = readl_relaxed(clk_base + PLLX_BASE);
0971 
0972         if (misc != tegra20_cpu_clk_sctx.pllx_misc ||
0973             base != tegra20_cpu_clk_sctx.pllx_base) {
0974             /* restore PLLX settings if CPU is on different PLL */
0975             writel(tegra20_cpu_clk_sctx.pllx_misc,
0976                         clk_base + PLLX_MISC);
0977             writel(tegra20_cpu_clk_sctx.pllx_base,
0978                         clk_base + PLLX_BASE);
0979 
0980             /* wait for PLL stabilization if PLLX was enabled */
0981             if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
0982                 udelay(300);
0983         }
0984     }
0985 
0986     /*
0987      * Restore original burst policy setting for calls resulting from CPU
0988      * LP2 in idle or system suspend.
0989      */
0990     writel(tegra20_cpu_clk_sctx.cclk_divider,
0991                     clk_base + SUPER_CCLK_DIVIDER);
0992     writel(tegra20_cpu_clk_sctx.cpu_burst,
0993                     clk_base + CCLK_BURST_POLICY);
0994 
0995     writel(tegra20_cpu_clk_sctx.clk_csite_src,
0996                     clk_base + CLK_SOURCE_CSITE);
0997 }
0998 #endif
0999 
1000 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1001     .wait_for_reset = tegra20_wait_cpu_in_reset,
1002     .put_in_reset   = tegra20_put_cpu_in_reset,
1003     .out_of_reset   = tegra20_cpu_out_of_reset,
1004     .enable_clock   = tegra20_enable_cpu_clock,
1005     .disable_clock  = tegra20_disable_cpu_clock,
1006 #ifdef CONFIG_PM_SLEEP
1007     .rail_off_ready = tegra20_cpu_rail_off_ready,
1008     .suspend    = tegra20_cpu_clock_suspend,
1009     .resume     = tegra20_cpu_clock_resume,
1010 #endif
1011 };
1012 
1013 static struct tegra_clk_init_table init_table[] = {
1014     { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
1015     { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
1016     { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
1017     { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
1018     { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
1019     { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
1020     { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 },
1021     { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 },
1022     { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 },
1023     { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
1024     { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
1025     { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1026     { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
1027     { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
1028     { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
1029     { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
1030     { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
1031     { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 0 },
1032     { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 0 },
1033     { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1034     { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1035     { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
1036     { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
1037     { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
1038     { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
1039     { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
1040     { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
1041     { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
1042     { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
1043     { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
1044     { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1045     { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1046     { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
1047     /* must be the last entry */
1048     { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
1049 };
1050 
1051 /*
1052  * Some clocks may be used by different drivers depending on the board
1053  * configuration.  List those here to register them twice in the clock lookup
1054  * table under two names.
1055  */
1056 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1057     TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "utmip-pad",     NULL),
1058     TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "tegra-ehci.0",  NULL),
1059     TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD,    "tegra-otg",     NULL),
1060     TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK,    NULL,           "cpu"),
1061     /* must be the last entry */
1062     TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL,            NULL),
1063 };
1064 
1065 static const struct of_device_id pmc_match[] __initconst = {
1066     { .compatible = "nvidia,tegra20-pmc" },
1067     { },
1068 };
1069 
1070 static bool tegra20_car_initialized;
1071 
1072 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
1073                            void *data)
1074 {
1075     struct clk_hw *parent_hw;
1076     struct clk_hw *hw;
1077     struct clk *clk;
1078 
1079     /*
1080      * Timer clocks are needed early, the rest of the clocks shouldn't be
1081      * available to device drivers until clock tree is fully initialized.
1082      */
1083     if (clkspec->args[0] != TEGRA20_CLK_RTC &&
1084         clkspec->args[0] != TEGRA20_CLK_TWD &&
1085         clkspec->args[0] != TEGRA20_CLK_TIMER &&
1086         !tegra20_car_initialized)
1087         return ERR_PTR(-EPROBE_DEFER);
1088 
1089     clk = of_clk_src_onecell_get(clkspec, data);
1090     if (IS_ERR(clk))
1091         return clk;
1092 
1093     hw = __clk_get_hw(clk);
1094 
1095     /*
1096      * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
1097      * clock is created by the pinctrl driver. It is possible for clk user
1098      * to request these clocks before pinctrl driver got probed and hence
1099      * user will get an orphaned clock. That might be undesirable because
1100      * user may expect parent clock to be enabled by the child.
1101      */
1102     if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
1103         clkspec->args[0] == TEGRA20_CLK_CDEV2) {
1104         parent_hw = clk_hw_get_parent(hw);
1105         if (!parent_hw)
1106             return ERR_PTR(-EPROBE_DEFER);
1107     }
1108 
1109     if (clkspec->args[0] == TEGRA20_CLK_EMC) {
1110         if (!tegra20_clk_emc_driver_available(hw))
1111             return ERR_PTR(-EPROBE_DEFER);
1112     }
1113 
1114     return clk;
1115 }
1116 
1117 static void __init tegra20_clock_init(struct device_node *np)
1118 {
1119     struct device_node *node;
1120 
1121     clk_base = of_iomap(np, 0);
1122     if (!clk_base) {
1123         pr_err("Can't map CAR registers\n");
1124         BUG();
1125     }
1126 
1127     node = of_find_matching_node(NULL, pmc_match);
1128     if (!node) {
1129         pr_err("Failed to find pmc node\n");
1130         BUG();
1131     }
1132 
1133     pmc_base = of_iomap(node, 0);
1134     if (!pmc_base) {
1135         pr_err("Can't map pmc registers\n");
1136         BUG();
1137     }
1138 
1139     clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1140                 TEGRA20_CLK_PERIPH_BANKS);
1141     if (!clks)
1142         return;
1143 
1144     tegra20_osc_clk_init();
1145     tegra_fixed_clk_init(tegra20_clks);
1146     tegra20_pll_init();
1147     tegra20_super_clk_init();
1148     tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1149     tegra20_periph_clk_init();
1150     tegra20_audio_clk_init();
1151 
1152     tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1153 
1154     tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
1155 
1156     tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1157 }
1158 CLK_OF_DECLARE_DRIVER(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
1159 
1160 /*
1161  * Clocks that use runtime PM can't be created at the tegra20_clock_init
1162  * time because drivers' base isn't initialized yet, and thus platform
1163  * devices can't be created for the clocks.  Hence we need to split the
1164  * registration of the clocks into two phases.  The first phase registers
1165  * essential clocks which don't require RPM and are actually used during
1166  * early boot.  The second phase registers clocks which use RPM and this
1167  * is done when device drivers' core API is ready.
1168  */
1169 static int tegra20_car_probe(struct platform_device *pdev)
1170 {
1171     struct clk *clk;
1172 
1173     clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1174                   ARRAY_SIZE(sclk_parents),
1175                   CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1176                   clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
1177     clks[TEGRA20_CLK_SCLK] = clk;
1178 
1179     tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1180     tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1181     tegra20_car_initialized = true;
1182 
1183     return 0;
1184 }
1185 
1186 static const struct of_device_id tegra20_car_match[] = {
1187     { .compatible = "nvidia,tegra20-car" },
1188     { }
1189 };
1190 
1191 static struct platform_driver tegra20_car_driver = {
1192     .driver = {
1193         .name = "tegra20-car",
1194         .of_match_table = tegra20_car_match,
1195         .suppress_bind_attrs = true,
1196     },
1197     .probe = tegra20_car_probe,
1198 };
1199 builtin_platform_driver(tegra20_car_driver);
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