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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/io.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/clkdev.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/delay.h>
0012 #include <linux/export.h>
0013 #include <linux/clk/tegra.h>
0014 #include <dt-bindings/clock/tegra124-car.h>
0015 #include <dt-bindings/reset/tegra124-car.h>
0016 
0017 #include "clk.h"
0018 #include "clk-id.h"
0019 
0020 /*
0021  * TEGRA124_CAR_BANK_COUNT: the number of peripheral clock register
0022  * banks present in the Tegra124/132 CAR IP block.  The banks are
0023  * identified by single letters, e.g.: L, H, U, V, W, X.  See
0024  * periph_regs[] in drivers/clk/tegra/clk.c
0025  */
0026 #define TEGRA124_CAR_BANK_COUNT         6
0027 
0028 #define CLK_SOURCE_CSITE 0x1d4
0029 #define CLK_SOURCE_EMC 0x19c
0030 #define CLK_SOURCE_SOR0 0x414
0031 
0032 #define RST_DFLL_DVCO           0x2f4
0033 #define DVFS_DFLL_RESET_SHIFT       0
0034 
0035 #define PLLC_BASE 0x80
0036 #define PLLC_OUT 0x84
0037 #define PLLC_MISC2 0x88
0038 #define PLLC_MISC 0x8c
0039 #define PLLC2_BASE 0x4e8
0040 #define PLLC2_MISC 0x4ec
0041 #define PLLC3_BASE 0x4fc
0042 #define PLLC3_MISC 0x500
0043 #define PLLM_BASE 0x90
0044 #define PLLM_OUT 0x94
0045 #define PLLM_MISC 0x9c
0046 #define PLLP_BASE 0xa0
0047 #define PLLP_MISC 0xac
0048 #define PLLA_BASE 0xb0
0049 #define PLLA_MISC 0xbc
0050 #define PLLD_BASE 0xd0
0051 #define PLLD_MISC 0xdc
0052 #define PLLU_BASE 0xc0
0053 #define PLLU_MISC 0xcc
0054 #define PLLX_BASE 0xe0
0055 #define PLLX_MISC 0xe4
0056 #define PLLX_MISC2 0x514
0057 #define PLLX_MISC3 0x518
0058 #define PLLE_BASE 0xe8
0059 #define PLLE_MISC 0xec
0060 #define PLLD2_BASE 0x4b8
0061 #define PLLD2_MISC 0x4bc
0062 #define PLLE_AUX 0x48c
0063 #define PLLRE_BASE 0x4c4
0064 #define PLLRE_MISC 0x4c8
0065 #define PLLDP_BASE 0x590
0066 #define PLLDP_MISC 0x594
0067 #define PLLC4_BASE 0x5a4
0068 #define PLLC4_MISC 0x5a8
0069 
0070 #define PLLC_IDDQ_BIT 26
0071 #define PLLRE_IDDQ_BIT 16
0072 #define PLLSS_IDDQ_BIT 19
0073 
0074 #define PLL_BASE_LOCK BIT(27)
0075 #define PLLE_MISC_LOCK BIT(11)
0076 #define PLLRE_MISC_LOCK BIT(24)
0077 
0078 #define PLL_MISC_LOCK_ENABLE 18
0079 #define PLLC_MISC_LOCK_ENABLE 24
0080 #define PLLDU_MISC_LOCK_ENABLE 22
0081 #define PLLE_MISC_LOCK_ENABLE 9
0082 #define PLLRE_MISC_LOCK_ENABLE 30
0083 #define PLLSS_MISC_LOCK_ENABLE 30
0084 
0085 #define PLLXC_SW_MAX_P 6
0086 
0087 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
0088 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
0089 
0090 #define CCLKG_BURST_POLICY 0x368
0091 
0092 /* Tegra CPU clock and reset control regs */
0093 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
0094 
0095 #define MASK(x) (BIT(x) - 1)
0096 
0097 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)  \
0098     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
0099                   29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
0100                   0, TEGRA_PERIPH_NO_GATE, _clk_id,\
0101                   _parents##_idx, 0, _lock)
0102 
0103 #define NODIV(_name, _parents, _offset, \
0104                   _mux_shift, _mux_mask, _clk_num, \
0105                   _gate_flags, _clk_id, _lock)      \
0106     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0107             _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
0108             _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
0109             _clk_id, _parents##_idx, 0, _lock)
0110 
0111 #ifdef CONFIG_PM_SLEEP
0112 static struct cpu_clk_suspend_context {
0113     u32 clk_csite_src;
0114     u32 cclkg_burst;
0115     u32 cclkg_divider;
0116 } tegra124_cpu_clk_sctx;
0117 #endif
0118 
0119 static void __iomem *clk_base;
0120 static void __iomem *pmc_base;
0121 
0122 static unsigned long osc_freq;
0123 static unsigned long pll_ref_freq;
0124 
0125 static DEFINE_SPINLOCK(pll_d_lock);
0126 static DEFINE_SPINLOCK(pll_e_lock);
0127 static DEFINE_SPINLOCK(pll_re_lock);
0128 static DEFINE_SPINLOCK(pll_u_lock);
0129 static DEFINE_SPINLOCK(emc_lock);
0130 static DEFINE_SPINLOCK(sor0_lock);
0131 
0132 /* possible OSC frequencies in Hz */
0133 static unsigned long tegra124_input_freq[] = {
0134     [ 0] = 13000000,
0135     [ 1] = 16800000,
0136     [ 4] = 19200000,
0137     [ 5] = 38400000,
0138     [ 8] = 12000000,
0139     [ 9] = 48000000,
0140     [12] = 26000000,
0141 };
0142 
0143 static struct div_nmp pllxc_nmp = {
0144     .divm_shift = 0,
0145     .divm_width = 8,
0146     .divn_shift = 8,
0147     .divn_width = 8,
0148     .divp_shift = 20,
0149     .divp_width = 4,
0150 };
0151 
0152 static const struct pdiv_map pllxc_p[] = {
0153     { .pdiv =  1, .hw_val =  0 },
0154     { .pdiv =  2, .hw_val =  1 },
0155     { .pdiv =  3, .hw_val =  2 },
0156     { .pdiv =  4, .hw_val =  3 },
0157     { .pdiv =  5, .hw_val =  4 },
0158     { .pdiv =  6, .hw_val =  5 },
0159     { .pdiv =  8, .hw_val =  6 },
0160     { .pdiv = 10, .hw_val =  7 },
0161     { .pdiv = 12, .hw_val =  8 },
0162     { .pdiv = 16, .hw_val =  9 },
0163     { .pdiv = 12, .hw_val = 10 },
0164     { .pdiv = 16, .hw_val = 11 },
0165     { .pdiv = 20, .hw_val = 12 },
0166     { .pdiv = 24, .hw_val = 13 },
0167     { .pdiv = 32, .hw_val = 14 },
0168     { .pdiv =  0, .hw_val =  0 },
0169 };
0170 
0171 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
0172     /* 1 GHz */
0173     { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
0174     { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
0175     { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
0176     { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
0177     { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
0178     {        0,          0,  0, 0, 0, 0 },
0179 };
0180 
0181 static struct tegra_clk_pll_params pll_x_params = {
0182     .input_min = 12000000,
0183     .input_max = 800000000,
0184     .cf_min = 12000000,
0185     .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
0186     .vco_min = 700000000,
0187     .vco_max = 3000000000UL,
0188     .base_reg = PLLX_BASE,
0189     .misc_reg = PLLX_MISC,
0190     .lock_mask = PLL_BASE_LOCK,
0191     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0192     .lock_delay = 300,
0193     .iddq_reg = PLLX_MISC3,
0194     .iddq_bit_idx = 3,
0195     .max_p = 6,
0196     .dyn_ramp_reg = PLLX_MISC2,
0197     .stepa_shift = 16,
0198     .stepb_shift = 24,
0199     .pdiv_tohw = pllxc_p,
0200     .div_nmp = &pllxc_nmp,
0201     .freq_table = pll_x_freq_table,
0202     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0203 };
0204 
0205 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
0206     { 12000000, 624000000, 104, 1, 2, 0 },
0207     { 12000000, 600000000, 100, 1, 2, 0 },
0208     { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
0209     { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
0210     { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
0211     { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
0212     {        0,         0,   0, 0, 0, 0 },
0213 };
0214 
0215 static struct tegra_clk_pll_params pll_c_params = {
0216     .input_min = 12000000,
0217     .input_max = 800000000,
0218     .cf_min = 12000000,
0219     .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
0220     .vco_min = 600000000,
0221     .vco_max = 1400000000,
0222     .base_reg = PLLC_BASE,
0223     .misc_reg = PLLC_MISC,
0224     .lock_mask = PLL_BASE_LOCK,
0225     .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
0226     .lock_delay = 300,
0227     .iddq_reg = PLLC_MISC,
0228     .iddq_bit_idx = PLLC_IDDQ_BIT,
0229     .max_p = PLLXC_SW_MAX_P,
0230     .dyn_ramp_reg = PLLC_MISC2,
0231     .stepa_shift = 17,
0232     .stepb_shift = 9,
0233     .pdiv_tohw = pllxc_p,
0234     .div_nmp = &pllxc_nmp,
0235     .freq_table = pll_c_freq_table,
0236     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0237 };
0238 
0239 static struct div_nmp pllcx_nmp = {
0240     .divm_shift = 0,
0241     .divm_width = 2,
0242     .divn_shift = 8,
0243     .divn_width = 8,
0244     .divp_shift = 20,
0245     .divp_width = 3,
0246 };
0247 
0248 static const struct pdiv_map pllc_p[] = {
0249     { .pdiv =  1, .hw_val = 0 },
0250     { .pdiv =  2, .hw_val = 1 },
0251     { .pdiv =  3, .hw_val = 2 },
0252     { .pdiv =  4, .hw_val = 3 },
0253     { .pdiv =  6, .hw_val = 4 },
0254     { .pdiv =  8, .hw_val = 5 },
0255     { .pdiv = 12, .hw_val = 6 },
0256     { .pdiv = 16, .hw_val = 7 },
0257     { .pdiv =  0, .hw_val = 0 },
0258 };
0259 
0260 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
0261     { 12000000, 600000000, 100, 1, 2, 0 },
0262     { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
0263     { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
0264     { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
0265     { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
0266     {        0,         0,   0, 0, 0, 0 },
0267 };
0268 
0269 static struct tegra_clk_pll_params pll_c2_params = {
0270     .input_min = 12000000,
0271     .input_max = 48000000,
0272     .cf_min = 12000000,
0273     .cf_max = 19200000,
0274     .vco_min = 600000000,
0275     .vco_max = 1200000000,
0276     .base_reg = PLLC2_BASE,
0277     .misc_reg = PLLC2_MISC,
0278     .lock_mask = PLL_BASE_LOCK,
0279     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0280     .lock_delay = 300,
0281     .pdiv_tohw = pllc_p,
0282     .div_nmp = &pllcx_nmp,
0283     .max_p = 7,
0284     .ext_misc_reg[0] = 0x4f0,
0285     .ext_misc_reg[1] = 0x4f4,
0286     .ext_misc_reg[2] = 0x4f8,
0287     .freq_table = pll_cx_freq_table,
0288     .flags = TEGRA_PLL_USE_LOCK,
0289 };
0290 
0291 static struct tegra_clk_pll_params pll_c3_params = {
0292     .input_min = 12000000,
0293     .input_max = 48000000,
0294     .cf_min = 12000000,
0295     .cf_max = 19200000,
0296     .vco_min = 600000000,
0297     .vco_max = 1200000000,
0298     .base_reg = PLLC3_BASE,
0299     .misc_reg = PLLC3_MISC,
0300     .lock_mask = PLL_BASE_LOCK,
0301     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0302     .lock_delay = 300,
0303     .pdiv_tohw = pllc_p,
0304     .div_nmp = &pllcx_nmp,
0305     .max_p = 7,
0306     .ext_misc_reg[0] = 0x504,
0307     .ext_misc_reg[1] = 0x508,
0308     .ext_misc_reg[2] = 0x50c,
0309     .freq_table = pll_cx_freq_table,
0310     .flags = TEGRA_PLL_USE_LOCK,
0311 };
0312 
0313 static struct div_nmp pllss_nmp = {
0314     .divm_shift = 0,
0315     .divm_width = 8,
0316     .divn_shift = 8,
0317     .divn_width = 8,
0318     .divp_shift = 20,
0319     .divp_width = 4,
0320 };
0321 
0322 static const struct pdiv_map pll12g_ssd_esd_p[] = {
0323     { .pdiv =  1, .hw_val =  0 },
0324     { .pdiv =  2, .hw_val =  1 },
0325     { .pdiv =  3, .hw_val =  2 },
0326     { .pdiv =  4, .hw_val =  3 },
0327     { .pdiv =  5, .hw_val =  4 },
0328     { .pdiv =  6, .hw_val =  5 },
0329     { .pdiv =  8, .hw_val =  6 },
0330     { .pdiv = 10, .hw_val =  7 },
0331     { .pdiv = 12, .hw_val =  8 },
0332     { .pdiv = 16, .hw_val =  9 },
0333     { .pdiv = 12, .hw_val = 10 },
0334     { .pdiv = 16, .hw_val = 11 },
0335     { .pdiv = 20, .hw_val = 12 },
0336     { .pdiv = 24, .hw_val = 13 },
0337     { .pdiv = 32, .hw_val = 14 },
0338     { .pdiv =  0, .hw_val =  0 },
0339 };
0340 
0341 static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
0342     { 12000000, 600000000, 100, 1, 2, 0 },
0343     { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
0344     { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
0345     { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
0346     { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
0347     {        0,         0,   0, 0, 0, 0 },
0348 };
0349 
0350 static struct tegra_clk_pll_params pll_c4_params = {
0351     .input_min = 12000000,
0352     .input_max = 1000000000,
0353     .cf_min = 12000000,
0354     .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
0355     .vco_min = 600000000,
0356     .vco_max = 1200000000,
0357     .base_reg = PLLC4_BASE,
0358     .misc_reg = PLLC4_MISC,
0359     .lock_mask = PLL_BASE_LOCK,
0360     .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
0361     .lock_delay = 300,
0362     .iddq_reg = PLLC4_BASE,
0363     .iddq_bit_idx = PLLSS_IDDQ_BIT,
0364     .pdiv_tohw = pll12g_ssd_esd_p,
0365     .div_nmp = &pllss_nmp,
0366     .ext_misc_reg[0] = 0x5ac,
0367     .ext_misc_reg[1] = 0x5b0,
0368     .ext_misc_reg[2] = 0x5b4,
0369     .freq_table = pll_c4_freq_table,
0370     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0371 };
0372 
0373 static const struct pdiv_map pllm_p[] = {
0374     { .pdiv =  1, .hw_val =  0 },
0375     { .pdiv =  2, .hw_val =  1 },
0376     { .pdiv =  3, .hw_val =  2 },
0377     { .pdiv =  4, .hw_val =  3 },
0378     { .pdiv =  5, .hw_val =  4 },
0379     { .pdiv =  6, .hw_val =  5 },
0380     { .pdiv =  8, .hw_val =  6 },
0381     { .pdiv = 10, .hw_val =  7 },
0382     { .pdiv = 12, .hw_val =  8 },
0383     { .pdiv = 16, .hw_val =  9 },
0384     { .pdiv = 12, .hw_val = 10 },
0385     { .pdiv = 16, .hw_val = 11 },
0386     { .pdiv = 20, .hw_val = 12 },
0387     { .pdiv = 24, .hw_val = 13 },
0388     { .pdiv = 32, .hw_val = 14 },
0389     { .pdiv =  0, .hw_val =  0 },
0390 };
0391 
0392 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
0393     { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
0394     { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
0395     { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
0396     { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
0397     { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
0398     {        0,         0,  0, 0, 0, 0},
0399 };
0400 
0401 static struct div_nmp pllm_nmp = {
0402     .divm_shift = 0,
0403     .divm_width = 8,
0404     .override_divm_shift = 0,
0405     .divn_shift = 8,
0406     .divn_width = 8,
0407     .override_divn_shift = 8,
0408     .divp_shift = 20,
0409     .divp_width = 1,
0410     .override_divp_shift = 27,
0411 };
0412 
0413 static struct tegra_clk_pll_params pll_m_params = {
0414     .input_min = 12000000,
0415     .input_max = 500000000,
0416     .cf_min = 12000000,
0417     .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
0418     .vco_min = 400000000,
0419     .vco_max = 1066000000,
0420     .base_reg = PLLM_BASE,
0421     .misc_reg = PLLM_MISC,
0422     .lock_mask = PLL_BASE_LOCK,
0423     .lock_delay = 300,
0424     .max_p = 5,
0425     .pdiv_tohw = pllm_p,
0426     .div_nmp = &pllm_nmp,
0427     .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
0428     .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
0429     .freq_table = pll_m_freq_table,
0430     .flags = TEGRA_PLL_USE_LOCK,
0431 };
0432 
0433 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
0434     /* PLLE special case: use cpcon field to store cml divider value */
0435     { 336000000, 100000000, 100, 21, 16, 11 },
0436     { 312000000, 100000000, 200, 26, 24, 13 },
0437     {  13000000, 100000000, 200,  1, 26, 13 },
0438     {  12000000, 100000000, 200,  1, 24, 13 },
0439     {         0,         0,   0,  0,  0,  0 },
0440 };
0441 
0442 static const struct pdiv_map plle_p[] = {
0443     { .pdiv =  1, .hw_val =  0 },
0444     { .pdiv =  2, .hw_val =  1 },
0445     { .pdiv =  3, .hw_val =  2 },
0446     { .pdiv =  4, .hw_val =  3 },
0447     { .pdiv =  5, .hw_val =  4 },
0448     { .pdiv =  6, .hw_val =  5 },
0449     { .pdiv =  8, .hw_val =  6 },
0450     { .pdiv = 10, .hw_val =  7 },
0451     { .pdiv = 12, .hw_val =  8 },
0452     { .pdiv = 16, .hw_val =  9 },
0453     { .pdiv = 12, .hw_val = 10 },
0454     { .pdiv = 16, .hw_val = 11 },
0455     { .pdiv = 20, .hw_val = 12 },
0456     { .pdiv = 24, .hw_val = 13 },
0457     { .pdiv = 32, .hw_val = 14 },
0458     { .pdiv =  1, .hw_val =  0 },
0459 };
0460 
0461 static struct div_nmp plle_nmp = {
0462     .divm_shift = 0,
0463     .divm_width = 8,
0464     .divn_shift = 8,
0465     .divn_width = 8,
0466     .divp_shift = 24,
0467     .divp_width = 4,
0468 };
0469 
0470 static struct tegra_clk_pll_params pll_e_params = {
0471     .input_min = 12000000,
0472     .input_max = 1000000000,
0473     .cf_min = 12000000,
0474     .cf_max = 75000000,
0475     .vco_min = 1600000000,
0476     .vco_max = 2400000000U,
0477     .base_reg = PLLE_BASE,
0478     .misc_reg = PLLE_MISC,
0479     .aux_reg = PLLE_AUX,
0480     .lock_mask = PLLE_MISC_LOCK,
0481     .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
0482     .lock_delay = 300,
0483     .pdiv_tohw = plle_p,
0484     .div_nmp = &plle_nmp,
0485     .freq_table = pll_e_freq_table,
0486     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
0487     .fixed_rate = 100000000,
0488 };
0489 
0490 static const struct clk_div_table pll_re_div_table[] = {
0491     { .val = 0, .div = 1 },
0492     { .val = 1, .div = 2 },
0493     { .val = 2, .div = 3 },
0494     { .val = 3, .div = 4 },
0495     { .val = 4, .div = 5 },
0496     { .val = 5, .div = 6 },
0497     { .val = 0, .div = 0 },
0498 };
0499 
0500 static struct div_nmp pllre_nmp = {
0501     .divm_shift = 0,
0502     .divm_width = 8,
0503     .divn_shift = 8,
0504     .divn_width = 8,
0505     .divp_shift = 16,
0506     .divp_width = 4,
0507 };
0508 
0509 static struct tegra_clk_pll_params pll_re_vco_params = {
0510     .input_min = 12000000,
0511     .input_max = 1000000000,
0512     .cf_min = 12000000,
0513     .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
0514     .vco_min = 300000000,
0515     .vco_max = 600000000,
0516     .base_reg = PLLRE_BASE,
0517     .misc_reg = PLLRE_MISC,
0518     .lock_mask = PLLRE_MISC_LOCK,
0519     .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
0520     .lock_delay = 300,
0521     .iddq_reg = PLLRE_MISC,
0522     .iddq_bit_idx = PLLRE_IDDQ_BIT,
0523     .div_nmp = &pllre_nmp,
0524     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
0525          TEGRA_PLL_LOCK_MISC,
0526 };
0527 
0528 static struct div_nmp pllp_nmp = {
0529     .divm_shift = 0,
0530     .divm_width = 5,
0531     .divn_shift = 8,
0532     .divn_width = 10,
0533     .divp_shift = 20,
0534     .divp_width = 3,
0535 };
0536 
0537 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
0538     { 12000000, 408000000, 408, 12, 1, 8 },
0539     { 13000000, 408000000, 408, 13, 1, 8 },
0540     { 16800000, 408000000, 340, 14, 1, 8 },
0541     { 19200000, 408000000, 340, 16, 1, 8 },
0542     { 26000000, 408000000, 408, 26, 1, 8 },
0543     {        0,         0,   0,  0, 0, 0 },
0544 };
0545 
0546 static struct tegra_clk_pll_params pll_p_params = {
0547     .input_min = 2000000,
0548     .input_max = 31000000,
0549     .cf_min = 1000000,
0550     .cf_max = 6000000,
0551     .vco_min = 200000000,
0552     .vco_max = 700000000,
0553     .base_reg = PLLP_BASE,
0554     .misc_reg = PLLP_MISC,
0555     .lock_mask = PLL_BASE_LOCK,
0556     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0557     .lock_delay = 300,
0558     .div_nmp = &pllp_nmp,
0559     .freq_table = pll_p_freq_table,
0560     .fixed_rate = 408000000,
0561     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
0562          TEGRA_PLL_HAS_LOCK_ENABLE,
0563 };
0564 
0565 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
0566     {  9600000, 282240000, 147,  5, 1, 4 },
0567     {  9600000, 368640000, 192,  5, 1, 4 },
0568     {  9600000, 240000000, 200,  8, 1, 8 },
0569     { 28800000, 282240000, 245, 25, 1, 8 },
0570     { 28800000, 368640000, 320, 25, 1, 8 },
0571     { 28800000, 240000000, 200, 24, 1, 8 },
0572     {        0,         0,   0,  0, 0, 0 },
0573 };
0574 
0575 static struct tegra_clk_pll_params pll_a_params = {
0576     .input_min = 2000000,
0577     .input_max = 31000000,
0578     .cf_min = 1000000,
0579     .cf_max = 6000000,
0580     .vco_min = 200000000,
0581     .vco_max = 700000000,
0582     .base_reg = PLLA_BASE,
0583     .misc_reg = PLLA_MISC,
0584     .lock_mask = PLL_BASE_LOCK,
0585     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0586     .lock_delay = 300,
0587     .div_nmp = &pllp_nmp,
0588     .freq_table = pll_a_freq_table,
0589     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
0590          TEGRA_PLL_HAS_LOCK_ENABLE,
0591 };
0592 
0593 static struct div_nmp plld_nmp = {
0594     .divm_shift = 0,
0595     .divm_width = 5,
0596     .divn_shift = 8,
0597     .divn_width = 11,
0598     .divp_shift = 20,
0599     .divp_width = 3,
0600 };
0601 
0602 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
0603     { 12000000,  216000000,  864, 12, 4, 12 },
0604     { 13000000,  216000000,  864, 13, 4, 12 },
0605     { 16800000,  216000000,  720, 14, 4, 12 },
0606     { 19200000,  216000000,  720, 16, 4, 12 },
0607     { 26000000,  216000000,  864, 26, 4, 12 },
0608     { 12000000,  594000000,  594, 12, 1, 12 },
0609     { 13000000,  594000000,  594, 13, 1, 12 },
0610     { 16800000,  594000000,  495, 14, 1, 12 },
0611     { 19200000,  594000000,  495, 16, 1, 12 },
0612     { 26000000,  594000000,  594, 26, 1, 12 },
0613     { 12000000, 1000000000, 1000, 12, 1, 12 },
0614     { 13000000, 1000000000, 1000, 13, 1, 12 },
0615     { 19200000, 1000000000,  625, 12, 1, 12 },
0616     { 26000000, 1000000000, 1000, 26, 1, 12 },
0617     {        0,          0,    0,  0, 0,  0 },
0618 };
0619 
0620 static struct tegra_clk_pll_params pll_d_params = {
0621     .input_min = 2000000,
0622     .input_max = 40000000,
0623     .cf_min = 1000000,
0624     .cf_max = 6000000,
0625     .vco_min = 500000000,
0626     .vco_max = 1000000000,
0627     .base_reg = PLLD_BASE,
0628     .misc_reg = PLLD_MISC,
0629     .lock_mask = PLL_BASE_LOCK,
0630     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0631     .lock_delay = 1000,
0632     .div_nmp = &plld_nmp,
0633     .freq_table = pll_d_freq_table,
0634     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0635          TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0636 };
0637 
0638 static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
0639     { 12000000, 594000000, 99, 1, 2, 0 },
0640     { 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
0641     { 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
0642     { 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
0643     { 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
0644     {        0,         0,  0, 0, 0, 0 },
0645 };
0646 
0647 static struct tegra_clk_pll_params tegra124_pll_d2_params = {
0648     .input_min = 12000000,
0649     .input_max = 1000000000,
0650     .cf_min = 12000000,
0651     .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
0652     .vco_min = 600000000,
0653     .vco_max = 1200000000,
0654     .base_reg = PLLD2_BASE,
0655     .misc_reg = PLLD2_MISC,
0656     .lock_mask = PLL_BASE_LOCK,
0657     .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
0658     .lock_delay = 300,
0659     .iddq_reg = PLLD2_BASE,
0660     .iddq_bit_idx = PLLSS_IDDQ_BIT,
0661     .pdiv_tohw = pll12g_ssd_esd_p,
0662     .div_nmp = &pllss_nmp,
0663     .ext_misc_reg[0] = 0x570,
0664     .ext_misc_reg[1] = 0x574,
0665     .ext_misc_reg[2] = 0x578,
0666     .max_p = 15,
0667     .freq_table = tegra124_pll_d2_freq_table,
0668     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0669 };
0670 
0671 static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
0672     { 12000000, 600000000, 100, 1, 2, 0 },
0673     { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
0674     { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
0675     { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
0676     { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
0677     {        0,         0,   0, 0, 0, 0 },
0678 };
0679 
0680 static struct tegra_clk_pll_params pll_dp_params = {
0681     .input_min = 12000000,
0682     .input_max = 1000000000,
0683     .cf_min = 12000000,
0684     .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
0685     .vco_min = 600000000,
0686     .vco_max = 1200000000,
0687     .base_reg = PLLDP_BASE,
0688     .misc_reg = PLLDP_MISC,
0689     .lock_mask = PLL_BASE_LOCK,
0690     .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE,
0691     .lock_delay = 300,
0692     .iddq_reg = PLLDP_BASE,
0693     .iddq_bit_idx = PLLSS_IDDQ_BIT,
0694     .pdiv_tohw = pll12g_ssd_esd_p,
0695     .div_nmp = &pllss_nmp,
0696     .ext_misc_reg[0] = 0x598,
0697     .ext_misc_reg[1] = 0x59c,
0698     .ext_misc_reg[2] = 0x5a0,
0699     .max_p = 5,
0700     .freq_table = pll_dp_freq_table,
0701     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0702 };
0703 
0704 static const struct pdiv_map pllu_p[] = {
0705     { .pdiv = 1, .hw_val = 1 },
0706     { .pdiv = 2, .hw_val = 0 },
0707     { .pdiv = 0, .hw_val = 0 },
0708 };
0709 
0710 static struct div_nmp pllu_nmp = {
0711     .divm_shift = 0,
0712     .divm_width = 5,
0713     .divn_shift = 8,
0714     .divn_width = 10,
0715     .divp_shift = 20,
0716     .divp_width = 1,
0717 };
0718 
0719 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
0720     { 12000000, 480000000, 960, 12, 2, 12 },
0721     { 13000000, 480000000, 960, 13, 2, 12 },
0722     { 16800000, 480000000, 400,  7, 2,  5 },
0723     { 19200000, 480000000, 200,  4, 2,  3 },
0724     { 26000000, 480000000, 960, 26, 2, 12 },
0725     {        0,         0,   0,  0, 0,  0 },
0726 };
0727 
0728 static struct tegra_clk_pll_params pll_u_params = {
0729     .input_min = 2000000,
0730     .input_max = 40000000,
0731     .cf_min = 1000000,
0732     .cf_max = 6000000,
0733     .vco_min = 480000000,
0734     .vco_max = 960000000,
0735     .base_reg = PLLU_BASE,
0736     .misc_reg = PLLU_MISC,
0737     .lock_mask = PLL_BASE_LOCK,
0738     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0739     .lock_delay = 1000,
0740     .pdiv_tohw = pllu_p,
0741     .div_nmp = &pllu_nmp,
0742     .freq_table = pll_u_freq_table,
0743     .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0744          TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0745 };
0746 
0747 static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
0748     [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
0749     [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
0750     [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
0751     [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
0752     [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
0753     [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
0754     [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
0755     [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
0756     [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
0757     [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
0758     [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
0759     [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
0760     [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
0761     [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
0762     [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
0763     [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
0764     [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
0765     [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
0766     [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
0767     [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
0768     [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
0769     [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
0770     [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
0771     [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
0772     [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
0773     [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
0774     [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
0775     [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
0776     [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
0777     [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
0778     [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
0779     [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
0780     [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
0781     [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
0782     [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
0783     [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
0784     [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
0785     [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
0786     [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
0787     [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
0788     [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
0789     [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
0790     [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
0791     [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
0792     [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
0793     [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
0794     [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
0795     [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
0796     [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
0797     [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
0798     [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
0799     [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
0800     [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
0801     [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
0802     [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
0803     [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
0804     [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
0805     [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
0806     [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
0807     [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
0808     [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
0809     [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
0810     [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
0811     [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
0812     [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
0813     [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
0814     [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
0815     [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
0816     [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
0817     [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
0818     [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
0819     [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
0820     [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
0821     [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
0822     [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
0823     [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
0824     [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
0825     [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
0826     [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
0827     [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
0828     [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
0829     [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
0830     [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
0831     [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
0832     [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
0833     [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
0834     [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
0835     [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
0836     [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
0837     [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
0838     [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
0839     [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
0840     [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
0841     [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
0842     [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
0843     [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
0844     [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
0845     [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
0846     [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
0847     [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
0848     [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
0849     [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
0850     [tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },
0851     [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
0852     [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
0853     [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
0854     [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
0855     [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
0856     [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
0857     [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
0858     [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
0859     [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
0860     [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
0861     [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
0862     [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
0863     [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
0864     [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
0865     [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
0866     [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
0867     [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
0868     [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
0869     [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
0870     [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
0871     [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
0872     [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
0873     [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
0874     [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
0875     [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
0876     [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
0877     [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
0878     [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
0879     [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
0880     [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
0881     [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
0882     [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
0883     [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
0884     [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
0885     [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
0886     [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
0887     [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
0888     [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
0889     [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
0890     [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
0891     [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
0892     [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
0893     [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
0894     [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
0895     [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
0896     [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
0897     [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
0898     [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
0899     [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
0900     [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
0901     [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
0902     [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
0903     [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
0904     [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
0905     [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
0906     [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
0907     [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
0908     [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
0909     [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
0910     [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
0911     [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
0912     [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
0913     [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
0914     [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
0915     [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
0916     [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
0917     [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
0918     [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
0919     [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
0920     [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
0921     [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
0922     [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
0923     [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
0924     [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
0925     [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
0926     [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
0927     [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
0928     [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
0929     [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
0930     [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
0931     [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
0932 };
0933 
0934 static struct tegra_devclk devclks[] __initdata = {
0935     { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M },
0936     { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
0937     { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K },
0938     { .con_id = "osc", .dt_id = TEGRA124_CLK_OSC },
0939     { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 },
0940     { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 },
0941     { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C },
0942     { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 },
0943     { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 },
0944     { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 },
0945     { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P },
0946     { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 },
0947     { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 },
0948     { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 },
0949     { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 },
0950     { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M },
0951     { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 },
0952     { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X },
0953     { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 },
0954     { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
0955     { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M },
0956     { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M },
0957     { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M },
0958     { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M },
0959     { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D },
0960     { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 },
0961     { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 },
0962     { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 },
0963     { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A },
0964     { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 },
0965     { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO },
0966     { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT },
0967     { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC },
0968     { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC },
0969     { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC },
0970     { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC },
0971     { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC },
0972     { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC },
0973     { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC },
0974     { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 },
0975     { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 },
0976     { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 },
0977     { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 },
0978     { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 },
0979     { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF },
0980     { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X },
0981     { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X },
0982     { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X },
0983     { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X },
0984     { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X },
0985     { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X },
0986     { .con_id = "extern1", .dt_id = TEGRA124_CLK_EXTERN1 },
0987     { .con_id = "extern2", .dt_id = TEGRA124_CLK_EXTERN2 },
0988     { .con_id = "extern3", .dt_id = TEGRA124_CLK_EXTERN3 },
0989     { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G },
0990     { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP },
0991     { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK },
0992     { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK },
0993     { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK },
0994     { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE },
0995     { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
0996     { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER },
0997     { .con_id = "hda", .dt_id = TEGRA124_CLK_HDA },
0998     { .con_id = "hda2codec_2x", .dt_id = TEGRA124_CLK_HDA2CODEC_2X },
0999     { .con_id = "hda2hdmi", .dt_id = TEGRA124_CLK_HDA2HDMI },
1000 };
1001 
1002 static const char * const sor0_parents[] = {
1003     "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
1004     "pll_d2_out0", "clk_m",
1005 };
1006 
1007 static const char * const sor0_out_parents[] = {
1008     "clk_m", "sor0_pad_clkout",
1009 };
1010 
1011 static struct tegra_periph_init_data tegra124_periph[] = {
1012     TEGRA_INIT_DATA_TABLE("sor0", NULL, NULL, sor0_parents,
1013                   CLK_SOURCE_SOR0, 29, 0x7, 0, 0, 0, 0,
1014                   0, 182, 0, tegra_clk_sor0, NULL, 0,
1015                   &sor0_lock),
1016     TEGRA_INIT_DATA_TABLE("sor0_out", NULL, NULL, sor0_out_parents,
1017                   CLK_SOURCE_SOR0, 14, 0x1, 0, 0, 0, 0,
1018                   0, 0, TEGRA_PERIPH_NO_GATE, tegra_clk_sor0_out,
1019                   NULL, 0, &sor0_lock),
1020 };
1021 
1022 static struct clk **clks;
1023 
1024 static __init void tegra124_periph_clk_init(void __iomem *clk_base,
1025                         void __iomem *pmc_base)
1026 {
1027     struct clk *clk;
1028     unsigned int i;
1029 
1030     /* xusb_ss_div2 */
1031     clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1032                     1, 2);
1033     clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
1034 
1035     clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
1036                           1, 17, 181);
1037     clks[TEGRA124_CLK_DPAUX] = clk;
1038 
1039     clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
1040                 clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
1041     clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;
1042 
1043     clk = tegra_clk_register_periph_gate("dsia", "pll_d_dsi_out", 0,
1044                          clk_base, 0, 48,
1045                          periph_clk_enb_refcnt);
1046     clks[TEGRA124_CLK_DSIA] = clk;
1047 
1048     clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0,
1049                          clk_base, 0, 82,
1050                          periph_clk_enb_refcnt);
1051     clks[TEGRA124_CLK_DSIB] = clk;
1052 
1053     clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
1054                     &emc_lock);
1055     clks[TEGRA124_CLK_MC] = clk;
1056 
1057     /* cml0 */
1058     clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1059                 0, 0, &pll_e_lock);
1060     clk_register_clkdev(clk, "cml0", NULL);
1061     clks[TEGRA124_CLK_CML0] = clk;
1062 
1063     /* cml1 */
1064     clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1065                 1, 0, &pll_e_lock);
1066     clk_register_clkdev(clk, "cml1", NULL);
1067     clks[TEGRA124_CLK_CML1] = clk;
1068 
1069     for (i = 0; i < ARRAY_SIZE(tegra124_periph); i++) {
1070         struct tegra_periph_init_data *init = &tegra124_periph[i];
1071         struct clk **clkp;
1072 
1073         clkp = tegra_lookup_dt_id(init->clk_id, tegra124_clks);
1074         if (!clkp) {
1075             pr_warn("clock %u not found\n", init->clk_id);
1076             continue;
1077         }
1078 
1079         clk = tegra_clk_register_periph_data(clk_base, init);
1080         *clkp = clk;
1081     }
1082 
1083     tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params);
1084 }
1085 
1086 static void __init tegra124_pll_init(void __iomem *clk_base,
1087                      void __iomem *pmc)
1088 {
1089     struct clk *clk;
1090 
1091     /* PLLC */
1092     clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
1093             pmc, 0, &pll_c_params, NULL);
1094     clk_register_clkdev(clk, "pll_c", NULL);
1095     clks[TEGRA124_CLK_PLL_C] = clk;
1096 
1097     /* PLLC_OUT1 */
1098     clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
1099             clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1100             8, 8, 1, NULL);
1101     clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
1102                 clk_base + PLLC_OUT, 1, 0,
1103                 CLK_SET_RATE_PARENT, 0, NULL);
1104     clk_register_clkdev(clk, "pll_c_out1", NULL);
1105     clks[TEGRA124_CLK_PLL_C_OUT1] = clk;
1106 
1107     /* PLLC_UD */
1108     clk = clk_register_fixed_factor(NULL, "pll_c_ud", "pll_c",
1109                     CLK_SET_RATE_PARENT, 1, 1);
1110     clk_register_clkdev(clk, "pll_c_ud", NULL);
1111     clks[TEGRA124_CLK_PLL_C_UD] = clk;
1112 
1113     /* PLLC2 */
1114     clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
1115                  &pll_c2_params, NULL);
1116     clk_register_clkdev(clk, "pll_c2", NULL);
1117     clks[TEGRA124_CLK_PLL_C2] = clk;
1118 
1119     /* PLLC3 */
1120     clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
1121                  &pll_c3_params, NULL);
1122     clk_register_clkdev(clk, "pll_c3", NULL);
1123     clks[TEGRA124_CLK_PLL_C3] = clk;
1124 
1125     /* PLLM */
1126     clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
1127                  CLK_SET_RATE_GATE, &pll_m_params, NULL);
1128     clk_register_clkdev(clk, "pll_m", NULL);
1129     clks[TEGRA124_CLK_PLL_M] = clk;
1130 
1131     /* PLLM_OUT1 */
1132     clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
1133                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1134                 8, 8, 1, NULL);
1135     clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
1136                 clk_base + PLLM_OUT, 1, 0,
1137                 CLK_SET_RATE_PARENT, 0, NULL);
1138     clk_register_clkdev(clk, "pll_m_out1", NULL);
1139     clks[TEGRA124_CLK_PLL_M_OUT1] = clk;
1140 
1141     /* PLLM_UD */
1142     clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
1143                     CLK_SET_RATE_PARENT, 1, 1);
1144     clk_register_clkdev(clk, "pll_m_ud", NULL);
1145     clks[TEGRA124_CLK_PLL_M_UD] = clk;
1146 
1147     /* PLLU */
1148     clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
1149                            &pll_u_params, &pll_u_lock);
1150     clk_register_clkdev(clk, "pll_u", NULL);
1151     clks[TEGRA124_CLK_PLL_U] = clk;
1152 
1153     /* PLLU_480M */
1154     clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
1155                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
1156                 22, 0, &pll_u_lock);
1157     clk_register_clkdev(clk, "pll_u_480M", NULL);
1158     clks[TEGRA124_CLK_PLL_U_480M] = clk;
1159 
1160     /* PLLU_60M */
1161     clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
1162                     CLK_SET_RATE_PARENT, 1, 8);
1163     clk_register_clkdev(clk, "pll_u_60M", NULL);
1164     clks[TEGRA124_CLK_PLL_U_60M] = clk;
1165 
1166     /* PLLU_48M */
1167     clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
1168                     CLK_SET_RATE_PARENT, 1, 10);
1169     clk_register_clkdev(clk, "pll_u_48M", NULL);
1170     clks[TEGRA124_CLK_PLL_U_48M] = clk;
1171 
1172     /* PLLU_12M */
1173     clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
1174                     CLK_SET_RATE_PARENT, 1, 40);
1175     clk_register_clkdev(clk, "pll_u_12M", NULL);
1176     clks[TEGRA124_CLK_PLL_U_12M] = clk;
1177 
1178     /* PLLD */
1179     clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
1180                 &pll_d_params, &pll_d_lock);
1181     clk_register_clkdev(clk, "pll_d", NULL);
1182     clks[TEGRA124_CLK_PLL_D] = clk;
1183 
1184     /* PLLD_OUT0 */
1185     clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
1186                     CLK_SET_RATE_PARENT, 1, 2);
1187     clk_register_clkdev(clk, "pll_d_out0", NULL);
1188     clks[TEGRA124_CLK_PLL_D_OUT0] = clk;
1189 
1190     /* PLLRE */
1191     clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1192                  0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
1193     clk_register_clkdev(clk, "pll_re_vco", NULL);
1194     clks[TEGRA124_CLK_PLL_RE_VCO] = clk;
1195 
1196     clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
1197                      clk_base + PLLRE_BASE, 16, 4, 0,
1198                      pll_re_div_table, &pll_re_lock);
1199     clk_register_clkdev(clk, "pll_re_out", NULL);
1200     clks[TEGRA124_CLK_PLL_RE_OUT] = clk;
1201 
1202     /* PLLE */
1203     clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref",
1204                       clk_base, 0, &pll_e_params, NULL);
1205     clk_register_clkdev(clk, "pll_e", NULL);
1206     clks[TEGRA124_CLK_PLL_E] = clk;
1207 
1208     /* PLLC4 */
1209     clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0,
1210                     &pll_c4_params, NULL);
1211     clk_register_clkdev(clk, "pll_c4", NULL);
1212     clks[TEGRA124_CLK_PLL_C4] = clk;
1213 
1214     /* PLLDP */
1215     clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0,
1216                     &pll_dp_params, NULL);
1217     clk_register_clkdev(clk, "pll_dp", NULL);
1218     clks[TEGRA124_CLK_PLL_DP] = clk;
1219 
1220     /* PLLD2 */
1221     clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0,
1222                     &tegra124_pll_d2_params, NULL);
1223     clk_register_clkdev(clk, "pll_d2", NULL);
1224     clks[TEGRA124_CLK_PLL_D2] = clk;
1225 
1226     /* PLLD2_OUT0 */
1227     clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
1228                     CLK_SET_RATE_PARENT, 1, 1);
1229     clk_register_clkdev(clk, "pll_d2_out0", NULL);
1230     clks[TEGRA124_CLK_PLL_D2_OUT0] = clk;
1231 
1232 }
1233 
1234 /* Tegra124 CPU clock and reset control functions */
1235 static void tegra124_wait_cpu_in_reset(u32 cpu)
1236 {
1237     unsigned int reg;
1238 
1239     do {
1240         reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1241         cpu_relax();
1242     } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1243 }
1244 
1245 static void tegra124_disable_cpu_clock(u32 cpu)
1246 {
1247     /* flow controller would take care in the power sequence. */
1248 }
1249 
1250 #ifdef CONFIG_PM_SLEEP
1251 static void tegra124_cpu_clock_suspend(void)
1252 {
1253     /* switch coresite to clk_m, save off original source */
1254     tegra124_cpu_clk_sctx.clk_csite_src =
1255                 readl(clk_base + CLK_SOURCE_CSITE);
1256     writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1257 
1258     tegra124_cpu_clk_sctx.cclkg_burst =
1259                 readl(clk_base + CCLKG_BURST_POLICY);
1260     tegra124_cpu_clk_sctx.cclkg_divider =
1261                 readl(clk_base + CCLKG_BURST_POLICY + 4);
1262 }
1263 
1264 static void tegra124_cpu_clock_resume(void)
1265 {
1266     writel(tegra124_cpu_clk_sctx.clk_csite_src,
1267                 clk_base + CLK_SOURCE_CSITE);
1268 
1269     writel(tegra124_cpu_clk_sctx.cclkg_burst,
1270                     clk_base + CCLKG_BURST_POLICY);
1271     writel(tegra124_cpu_clk_sctx.cclkg_divider,
1272                     clk_base + CCLKG_BURST_POLICY + 4);
1273 }
1274 #endif
1275 
1276 static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
1277     .wait_for_reset = tegra124_wait_cpu_in_reset,
1278     .disable_clock  = tegra124_disable_cpu_clock,
1279 #ifdef CONFIG_PM_SLEEP
1280     .suspend    = tegra124_cpu_clock_suspend,
1281     .resume     = tegra124_cpu_clock_resume,
1282 #endif
1283 };
1284 
1285 static const struct of_device_id pmc_match[] __initconst = {
1286     { .compatible = "nvidia,tegra124-pmc" },
1287     { },
1288 };
1289 
1290 static struct tegra_clk_init_table common_init_table[] __initdata = {
1291     { TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
1292     { TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
1293     { TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
1294     { TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
1295     { TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 282240000, 0 },
1296     { TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 0 },
1297     { TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1298     { TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1299     { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1300     { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1301     { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
1302     { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 },
1303     { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
1304     { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1305     { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
1306     { TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 0 },
1307     { TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
1308     { TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
1309     { TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
1310     { TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
1311     { TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
1312     { TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
1313     { TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
1314     { TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
1315     { TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
1316     { TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
1317     { TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
1318     { TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
1319     { TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
1320     { TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
1321     { TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
1322     { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
1323     { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
1324     { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
1325     { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 },
1326     { TEGRA124_CLK_SPDIF_IN_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1327     { TEGRA124_CLK_I2S0_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1328     { TEGRA124_CLK_I2S1_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1329     { TEGRA124_CLK_I2S2_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1330     { TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1331     { TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1332     { TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
1333     /* must be the last entry */
1334     { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1335 };
1336 
1337 static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
1338     { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
1339     { TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
1340     { TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
1341     { TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
1342     /* must be the last entry */
1343     { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1344 };
1345 
1346 /* Tegra132 requires the SOC_THERM clock to remain active */
1347 static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
1348     { TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
1349     /* must be the last entry */
1350     { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
1351 };
1352 
1353 static struct tegra_audio_clk_info tegra124_audio_plls[] = {
1354     { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1355 };
1356 
1357 /**
1358  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1359  *
1360  * Program an initial clock rate and enable or disable clocks needed
1361  * by the rest of the kernel, for Tegra124 SoCs.  It is intended to be
1362  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1363  * this will be called as an arch_initcall.  No return value.
1364  */
1365 static void __init tegra124_clock_apply_init_table(void)
1366 {
1367     tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1368     tegra_init_from_table(tegra124_init_table, clks, TEGRA124_CLK_CLK_MAX);
1369 }
1370 
1371 /**
1372  * tegra124_car_barrier - wait for pending writes to the CAR to complete
1373  *
1374  * Wait for any outstanding writes to the CAR MMIO space from this CPU
1375  * to complete before continuing execution.  No return value.
1376  */
1377 static void tegra124_car_barrier(void)
1378 {
1379     readl_relaxed(clk_base + RST_DFLL_DVCO);
1380 }
1381 
1382 /**
1383  * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1384  *
1385  * Assert the reset line of the DFLL's DVCO.  No return value.
1386  */
1387 static void tegra124_clock_assert_dfll_dvco_reset(void)
1388 {
1389     u32 v;
1390 
1391     v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1392     v |= (1 << DVFS_DFLL_RESET_SHIFT);
1393     writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1394     tegra124_car_barrier();
1395 }
1396 
1397 /**
1398  * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1399  *
1400  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1401  * operate.  No return value.
1402  */
1403 static void tegra124_clock_deassert_dfll_dvco_reset(void)
1404 {
1405     u32 v;
1406 
1407     v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1408     v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1409     writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1410     tegra124_car_barrier();
1411 }
1412 
1413 static int tegra124_reset_assert(unsigned long id)
1414 {
1415     if (id == TEGRA124_RST_DFLL_DVCO)
1416         tegra124_clock_assert_dfll_dvco_reset();
1417     else
1418         return -EINVAL;
1419 
1420     return 0;
1421 }
1422 
1423 static int tegra124_reset_deassert(unsigned long id)
1424 {
1425     if (id == TEGRA124_RST_DFLL_DVCO)
1426         tegra124_clock_deassert_dfll_dvco_reset();
1427     else
1428         return -EINVAL;
1429 
1430     return 0;
1431 }
1432 
1433 /**
1434  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1435  *
1436  * Program an initial clock rate and enable or disable clocks needed
1437  * by the rest of the kernel, for Tegra132 SoCs.  It is intended to be
1438  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1439  * this will be called as an arch_initcall.  No return value.
1440  */
1441 static void __init tegra132_clock_apply_init_table(void)
1442 {
1443     tegra_init_from_table(common_init_table, clks, TEGRA124_CLK_CLK_MAX);
1444     tegra_init_from_table(tegra132_init_table, clks, TEGRA124_CLK_CLK_MAX);
1445 }
1446 
1447 /**
1448  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1449  * @np: struct device_node * of the DT node for the SoC CAR IP block
1450  *
1451  * Register most of the clocks controlled by the CAR IP block.
1452  * Everything in this function should be common to Tegra124 and Tegra132.
1453  * No return value.
1454  */
1455 static void __init tegra124_132_clock_init_pre(struct device_node *np)
1456 {
1457     struct device_node *node;
1458     u32 plld_base;
1459 
1460     clk_base = of_iomap(np, 0);
1461     if (!clk_base) {
1462         pr_err("ioremap tegra124/tegra132 CAR failed\n");
1463         return;
1464     }
1465 
1466     node = of_find_matching_node(NULL, pmc_match);
1467     if (!node) {
1468         pr_err("Failed to find pmc node\n");
1469         WARN_ON(1);
1470         return;
1471     }
1472 
1473     pmc_base = of_iomap(node, 0);
1474     if (!pmc_base) {
1475         pr_err("Can't map pmc registers\n");
1476         WARN_ON(1);
1477         return;
1478     }
1479 
1480     clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX,
1481                   TEGRA124_CAR_BANK_COUNT);
1482     if (!clks)
1483         return;
1484 
1485     if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq,
1486                    ARRAY_SIZE(tegra124_input_freq), 1, &osc_freq,
1487                    &pll_ref_freq) < 0)
1488         return;
1489 
1490     tegra_fixed_clk_init(tegra124_clks);
1491     tegra124_pll_init(clk_base, pmc_base);
1492     tegra124_periph_clk_init(clk_base, pmc_base);
1493     tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks,
1494                  tegra124_audio_plls,
1495                  ARRAY_SIZE(tegra124_audio_plls), 24576000);
1496 
1497     /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
1498     plld_base = readl(clk_base + PLLD_BASE);
1499     plld_base &= ~BIT(25);
1500     writel(plld_base, clk_base + PLLD_BASE);
1501 }
1502 
1503 static struct clk *tegra124_clk_src_onecell_get(struct of_phandle_args *clkspec,
1504                         void *data)
1505 {
1506     struct clk_hw *hw;
1507     struct clk *clk;
1508 
1509     clk = of_clk_src_onecell_get(clkspec, data);
1510     if (IS_ERR(clk))
1511         return clk;
1512 
1513     hw = __clk_get_hw(clk);
1514 
1515     if (clkspec->args[0] == TEGRA124_CLK_EMC) {
1516         if (!tegra124_clk_emc_driver_available(hw))
1517             return ERR_PTR(-EPROBE_DEFER);
1518     }
1519 
1520     return clk;
1521 }
1522 
1523 /**
1524  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1525  * @np: struct device_node * of the DT node for the SoC CAR IP block
1526  *
1527  * Register most of the clocks controlled by the CAR IP block.
1528  * Everything in this function should be common to Tegra124
1529  * and Tegra132.  This function must be called after
1530  * tegra124_132_clock_init_pre(), otherwise clk_base will not be set.
1531  * No return value.
1532  */
1533 static void __init tegra124_132_clock_init_post(struct device_node *np)
1534 {
1535     tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks,
1536                   &pll_x_params);
1537     tegra_init_special_resets(1, tegra124_reset_assert,
1538                   tegra124_reset_deassert);
1539     tegra_add_of_provider(np, tegra124_clk_src_onecell_get);
1540 
1541     clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,
1542                                &emc_lock);
1543 
1544     tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1545 
1546     tegra_cpu_car_ops = &tegra124_cpu_car_ops;
1547 }
1548 
1549 /**
1550  * tegra124_clock_init - Tegra124-specific clock initialization
1551  * @np: struct device_node * of the DT node for the SoC CAR IP block
1552  *
1553  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1554  * this code is shared between the Tegra124 and Tegra132 SoCs,
1555  * although some of the initial clock settings and CPU clocks differ.
1556  * Intended to be called by the OF init code when a DT node with the
1557  * "nvidia,tegra124-car" string is encountered, and declared with
1558  * CLK_OF_DECLARE.  No return value.
1559  */
1560 static void __init tegra124_clock_init(struct device_node *np)
1561 {
1562     tegra124_132_clock_init_pre(np);
1563     tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
1564     tegra124_132_clock_init_post(np);
1565 }
1566 
1567 /**
1568  * tegra132_clock_init - Tegra132-specific clock initialization
1569  * @np: struct device_node * of the DT node for the SoC CAR IP block
1570  *
1571  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1572  * this code is shared between the Tegra124 and Tegra132 SoCs,
1573  * although some of the initial clock settings and CPU clocks differ.
1574  * Intended to be called by the OF init code when a DT node with the
1575  * "nvidia,tegra132-car" string is encountered, and declared with
1576  * CLK_OF_DECLARE.  No return value.
1577  */
1578 static void __init tegra132_clock_init(struct device_node *np)
1579 {
1580     tegra124_132_clock_init_pre(np);
1581 
1582     /*
1583      * On Tegra132, these clocks are controlled by the
1584      * CLUSTER_clocks IP block, located in the CPU complex
1585      */
1586     tegra124_clks[tegra_clk_cclk_g].present = false;
1587     tegra124_clks[tegra_clk_cclk_lp].present = false;
1588     tegra124_clks[tegra_clk_pll_x].present = false;
1589     tegra124_clks[tegra_clk_pll_x_out0].present = false;
1590 
1591     tegra_clk_apply_init_table = tegra132_clock_apply_init_table;
1592     tegra124_132_clock_init_post(np);
1593 }
1594 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1595 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);
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