Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/io.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/delay.h>
0011 #include <linux/export.h>
0012 #include <linux/clk/tegra.h>
0013 #include <dt-bindings/clock/tegra114-car.h>
0014 
0015 #include "clk.h"
0016 #include "clk-id.h"
0017 
0018 #define RST_DFLL_DVCO           0x2F4
0019 #define CPU_FINETRIM_SELECT     0x4d4   /* override default prop dlys */
0020 #define CPU_FINETRIM_DR         0x4d8   /* rise->rise prop dly A */
0021 #define CPU_FINETRIM_R          0x4e4   /* rise->rise prop dly inc A */
0022 
0023 /* RST_DFLL_DVCO bitfields */
0024 #define DVFS_DFLL_RESET_SHIFT       0
0025 
0026 /* CPU_FINETRIM_SELECT and CPU_FINETRIM_DR bitfields */
0027 #define CPU_FINETRIM_1_FCPU_1       BIT(0)  /* fcpu0 */
0028 #define CPU_FINETRIM_1_FCPU_2       BIT(1)  /* fcpu1 */
0029 #define CPU_FINETRIM_1_FCPU_3       BIT(2)  /* fcpu2 */
0030 #define CPU_FINETRIM_1_FCPU_4       BIT(3)  /* fcpu3 */
0031 #define CPU_FINETRIM_1_FCPU_5       BIT(4)  /* fl2 */
0032 #define CPU_FINETRIM_1_FCPU_6       BIT(5)  /* ftop */
0033 
0034 /* CPU_FINETRIM_R bitfields */
0035 #define CPU_FINETRIM_R_FCPU_1_SHIFT 0       /* fcpu0 */
0036 #define CPU_FINETRIM_R_FCPU_1_MASK  (0x3 << CPU_FINETRIM_R_FCPU_1_SHIFT)
0037 #define CPU_FINETRIM_R_FCPU_2_SHIFT 2       /* fcpu1 */
0038 #define CPU_FINETRIM_R_FCPU_2_MASK  (0x3 << CPU_FINETRIM_R_FCPU_2_SHIFT)
0039 #define CPU_FINETRIM_R_FCPU_3_SHIFT 4       /* fcpu2 */
0040 #define CPU_FINETRIM_R_FCPU_3_MASK  (0x3 << CPU_FINETRIM_R_FCPU_3_SHIFT)
0041 #define CPU_FINETRIM_R_FCPU_4_SHIFT 6       /* fcpu3 */
0042 #define CPU_FINETRIM_R_FCPU_4_MASK  (0x3 << CPU_FINETRIM_R_FCPU_4_SHIFT)
0043 #define CPU_FINETRIM_R_FCPU_5_SHIFT 8       /* fl2 */
0044 #define CPU_FINETRIM_R_FCPU_5_MASK  (0x3 << CPU_FINETRIM_R_FCPU_5_SHIFT)
0045 #define CPU_FINETRIM_R_FCPU_6_SHIFT 10      /* ftop */
0046 #define CPU_FINETRIM_R_FCPU_6_MASK  (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
0047 
0048 #define TEGRA114_CLK_PERIPH_BANKS   5
0049 
0050 #define PLLC_BASE 0x80
0051 #define PLLC_MISC2 0x88
0052 #define PLLC_MISC 0x8c
0053 #define PLLC2_BASE 0x4e8
0054 #define PLLC2_MISC 0x4ec
0055 #define PLLC3_BASE 0x4fc
0056 #define PLLC3_MISC 0x500
0057 #define PLLM_BASE 0x90
0058 #define PLLM_MISC 0x9c
0059 #define PLLP_BASE 0xa0
0060 #define PLLP_MISC 0xac
0061 #define PLLX_BASE 0xe0
0062 #define PLLX_MISC 0xe4
0063 #define PLLX_MISC2 0x514
0064 #define PLLX_MISC3 0x518
0065 #define PLLD_BASE 0xd0
0066 #define PLLD_MISC 0xdc
0067 #define PLLD2_BASE 0x4b8
0068 #define PLLD2_MISC 0x4bc
0069 #define PLLE_BASE 0xe8
0070 #define PLLE_MISC 0xec
0071 #define PLLA_BASE 0xb0
0072 #define PLLA_MISC 0xbc
0073 #define PLLU_BASE 0xc0
0074 #define PLLU_MISC 0xcc
0075 #define PLLRE_BASE 0x4c4
0076 #define PLLRE_MISC 0x4c8
0077 
0078 #define PLL_MISC_LOCK_ENABLE 18
0079 #define PLLC_MISC_LOCK_ENABLE 24
0080 #define PLLDU_MISC_LOCK_ENABLE 22
0081 #define PLLE_MISC_LOCK_ENABLE 9
0082 #define PLLRE_MISC_LOCK_ENABLE 30
0083 
0084 #define PLLC_IDDQ_BIT 26
0085 #define PLLX_IDDQ_BIT 3
0086 #define PLLRE_IDDQ_BIT 16
0087 
0088 #define PLL_BASE_LOCK BIT(27)
0089 #define PLLE_MISC_LOCK BIT(11)
0090 #define PLLRE_MISC_LOCK BIT(24)
0091 #define PLLCX_BASE_LOCK (BIT(26)|BIT(27))
0092 
0093 #define PLLE_AUX 0x48c
0094 #define PLLC_OUT 0x84
0095 #define PLLM_OUT 0x94
0096 
0097 #define OSC_CTRL            0x50
0098 #define OSC_CTRL_OSC_FREQ_SHIFT     28
0099 #define OSC_CTRL_PLL_REF_DIV_SHIFT  26
0100 
0101 #define PLLXC_SW_MAX_P          6
0102 
0103 #define CCLKG_BURST_POLICY 0x368
0104 
0105 #define CLK_SOURCE_CSITE 0x1d4
0106 #define CLK_SOURCE_EMC 0x19c
0107 
0108 /* PLLM override registers */
0109 #define PMC_PLLM_WB0_OVERRIDE 0x1dc
0110 #define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
0111 
0112 /* Tegra CPU clock and reset control regs */
0113 #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
0114 
0115 #define MUX8(_name, _parents, _offset, \
0116                  _clk_num, _gate_flags, _clk_id)    \
0117     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0118             29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
0119             _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
0120             NULL)
0121 
0122 #ifdef CONFIG_PM_SLEEP
0123 static struct cpu_clk_suspend_context {
0124     u32 clk_csite_src;
0125     u32 cclkg_burst;
0126     u32 cclkg_divider;
0127 } tegra114_cpu_clk_sctx;
0128 #endif
0129 
0130 static void __iomem *clk_base;
0131 static void __iomem *pmc_base;
0132 
0133 static DEFINE_SPINLOCK(pll_d_lock);
0134 static DEFINE_SPINLOCK(pll_d2_lock);
0135 static DEFINE_SPINLOCK(pll_u_lock);
0136 static DEFINE_SPINLOCK(pll_re_lock);
0137 static DEFINE_SPINLOCK(emc_lock);
0138 
0139 static struct div_nmp pllxc_nmp = {
0140     .divm_shift = 0,
0141     .divm_width = 8,
0142     .divn_shift = 8,
0143     .divn_width = 8,
0144     .divp_shift = 20,
0145     .divp_width = 4,
0146 };
0147 
0148 static const struct pdiv_map pllxc_p[] = {
0149     { .pdiv =  1, .hw_val =  0 },
0150     { .pdiv =  2, .hw_val =  1 },
0151     { .pdiv =  3, .hw_val =  2 },
0152     { .pdiv =  4, .hw_val =  3 },
0153     { .pdiv =  5, .hw_val =  4 },
0154     { .pdiv =  6, .hw_val =  5 },
0155     { .pdiv =  8, .hw_val =  6 },
0156     { .pdiv = 10, .hw_val =  7 },
0157     { .pdiv = 12, .hw_val =  8 },
0158     { .pdiv = 16, .hw_val =  9 },
0159     { .pdiv = 12, .hw_val = 10 },
0160     { .pdiv = 16, .hw_val = 11 },
0161     { .pdiv = 20, .hw_val = 12 },
0162     { .pdiv = 24, .hw_val = 13 },
0163     { .pdiv = 32, .hw_val = 14 },
0164     { .pdiv =  0, .hw_val =  0 },
0165 };
0166 
0167 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
0168     { 12000000, 624000000, 104, 1, 2, 0 },
0169     { 12000000, 600000000, 100, 1, 2, 0 },
0170     { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
0171     { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
0172     { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
0173     { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
0174     {        0,         0,   0, 0, 0, 0 },
0175 };
0176 
0177 static struct tegra_clk_pll_params pll_c_params = {
0178     .input_min = 12000000,
0179     .input_max = 800000000,
0180     .cf_min = 12000000,
0181     .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
0182     .vco_min = 600000000,
0183     .vco_max = 1400000000,
0184     .base_reg = PLLC_BASE,
0185     .misc_reg = PLLC_MISC,
0186     .lock_mask = PLL_BASE_LOCK,
0187     .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE,
0188     .lock_delay = 300,
0189     .iddq_reg = PLLC_MISC,
0190     .iddq_bit_idx = PLLC_IDDQ_BIT,
0191     .max_p = PLLXC_SW_MAX_P,
0192     .dyn_ramp_reg = PLLC_MISC2,
0193     .stepa_shift = 17,
0194     .stepb_shift = 9,
0195     .pdiv_tohw = pllxc_p,
0196     .div_nmp = &pllxc_nmp,
0197     .freq_table = pll_c_freq_table,
0198     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0199 };
0200 
0201 static struct div_nmp pllcx_nmp = {
0202     .divm_shift = 0,
0203     .divm_width = 2,
0204     .divn_shift = 8,
0205     .divn_width = 8,
0206     .divp_shift = 20,
0207     .divp_width = 3,
0208 };
0209 
0210 static const struct pdiv_map pllc_p[] = {
0211     { .pdiv =  1, .hw_val = 0 },
0212     { .pdiv =  2, .hw_val = 1 },
0213     { .pdiv =  4, .hw_val = 3 },
0214     { .pdiv =  8, .hw_val = 5 },
0215     { .pdiv = 16, .hw_val = 7 },
0216     { .pdiv =  0, .hw_val = 0 },
0217 };
0218 
0219 static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
0220     { 12000000, 600000000, 100, 1, 2, 0 },
0221     { 13000000, 600000000,  92, 1, 2, 0 }, /* actual: 598.0 MHz */
0222     { 16800000, 600000000,  71, 1, 2, 0 }, /* actual: 596.4 MHz */
0223     { 19200000, 600000000,  62, 1, 2, 0 }, /* actual: 595.2 MHz */
0224     { 26000000, 600000000,  92, 2, 2, 0 }, /* actual: 598.0 MHz */
0225     {        0,         0,   0, 0, 0, 0 },
0226 };
0227 
0228 static struct tegra_clk_pll_params pll_c2_params = {
0229     .input_min = 12000000,
0230     .input_max = 48000000,
0231     .cf_min = 12000000,
0232     .cf_max = 19200000,
0233     .vco_min = 600000000,
0234     .vco_max = 1200000000,
0235     .base_reg = PLLC2_BASE,
0236     .misc_reg = PLLC2_MISC,
0237     .lock_mask = PLL_BASE_LOCK,
0238     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0239     .lock_delay = 300,
0240     .pdiv_tohw = pllc_p,
0241     .div_nmp = &pllcx_nmp,
0242     .max_p = 7,
0243     .ext_misc_reg[0] = 0x4f0,
0244     .ext_misc_reg[1] = 0x4f4,
0245     .ext_misc_reg[2] = 0x4f8,
0246     .freq_table = pll_cx_freq_table,
0247     .flags = TEGRA_PLL_USE_LOCK,
0248 };
0249 
0250 static struct tegra_clk_pll_params pll_c3_params = {
0251     .input_min = 12000000,
0252     .input_max = 48000000,
0253     .cf_min = 12000000,
0254     .cf_max = 19200000,
0255     .vco_min = 600000000,
0256     .vco_max = 1200000000,
0257     .base_reg = PLLC3_BASE,
0258     .misc_reg = PLLC3_MISC,
0259     .lock_mask = PLL_BASE_LOCK,
0260     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0261     .lock_delay = 300,
0262     .pdiv_tohw = pllc_p,
0263     .div_nmp = &pllcx_nmp,
0264     .max_p = 7,
0265     .ext_misc_reg[0] = 0x504,
0266     .ext_misc_reg[1] = 0x508,
0267     .ext_misc_reg[2] = 0x50c,
0268     .freq_table = pll_cx_freq_table,
0269     .flags = TEGRA_PLL_USE_LOCK,
0270 };
0271 
0272 static struct div_nmp pllm_nmp = {
0273     .divm_shift = 0,
0274     .divm_width = 8,
0275     .override_divm_shift = 0,
0276     .divn_shift = 8,
0277     .divn_width = 8,
0278     .override_divn_shift = 8,
0279     .divp_shift = 20,
0280     .divp_width = 1,
0281     .override_divp_shift = 27,
0282 };
0283 
0284 static const struct pdiv_map pllm_p[] = {
0285     { .pdiv = 1, .hw_val = 0 },
0286     { .pdiv = 2, .hw_val = 1 },
0287     { .pdiv = 0, .hw_val = 0 },
0288 };
0289 
0290 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
0291     { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
0292     { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
0293     { 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
0294     { 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
0295     { 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
0296     {        0,         0,  0, 0, 0, 0 },
0297 };
0298 
0299 static struct tegra_clk_pll_params pll_m_params = {
0300     .input_min = 12000000,
0301     .input_max = 500000000,
0302     .cf_min = 12000000,
0303     .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
0304     .vco_min = 400000000,
0305     .vco_max = 1066000000,
0306     .base_reg = PLLM_BASE,
0307     .misc_reg = PLLM_MISC,
0308     .lock_mask = PLL_BASE_LOCK,
0309     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0310     .lock_delay = 300,
0311     .max_p = 2,
0312     .pdiv_tohw = pllm_p,
0313     .div_nmp = &pllm_nmp,
0314     .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
0315     .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2,
0316     .freq_table = pll_m_freq_table,
0317     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
0318          TEGRA_PLL_FIXED,
0319 };
0320 
0321 static struct div_nmp pllp_nmp = {
0322     .divm_shift = 0,
0323     .divm_width = 5,
0324     .divn_shift = 8,
0325     .divn_width = 10,
0326     .divp_shift = 20,
0327     .divp_width = 3,
0328 };
0329 
0330 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
0331     { 12000000, 216000000, 432, 12, 2, 8 },
0332     { 13000000, 216000000, 432, 13, 2, 8 },
0333     { 16800000, 216000000, 360, 14, 2, 8 },
0334     { 19200000, 216000000, 360, 16, 2, 8 },
0335     { 26000000, 216000000, 432, 26, 2, 8 },
0336     {        0,         0,   0,  0, 0, 0 },
0337 };
0338 
0339 static struct tegra_clk_pll_params pll_p_params = {
0340     .input_min = 2000000,
0341     .input_max = 31000000,
0342     .cf_min = 1000000,
0343     .cf_max = 6000000,
0344     .vco_min = 200000000,
0345     .vco_max = 700000000,
0346     .base_reg = PLLP_BASE,
0347     .misc_reg = PLLP_MISC,
0348     .lock_mask = PLL_BASE_LOCK,
0349     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0350     .lock_delay = 300,
0351     .div_nmp = &pllp_nmp,
0352     .freq_table = pll_p_freq_table,
0353     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK |
0354          TEGRA_PLL_HAS_LOCK_ENABLE,
0355     .fixed_rate = 408000000,
0356 };
0357 
0358 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
0359     {  9600000, 282240000, 147,  5, 1, 4 },
0360     {  9600000, 368640000, 192,  5, 1, 4 },
0361     {  9600000, 240000000, 200,  8, 1, 8 },
0362     { 28800000, 282240000, 245, 25, 1, 8 },
0363     { 28800000, 368640000, 320, 25, 1, 8 },
0364     { 28800000, 240000000, 200, 24, 1, 8 },
0365     {        0,         0,   0,  0, 0, 0 },
0366 };
0367 
0368 
0369 static struct tegra_clk_pll_params pll_a_params = {
0370     .input_min = 2000000,
0371     .input_max = 31000000,
0372     .cf_min = 1000000,
0373     .cf_max = 6000000,
0374     .vco_min = 200000000,
0375     .vco_max = 700000000,
0376     .base_reg = PLLA_BASE,
0377     .misc_reg = PLLA_MISC,
0378     .lock_mask = PLL_BASE_LOCK,
0379     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0380     .lock_delay = 300,
0381     .div_nmp = &pllp_nmp,
0382     .freq_table = pll_a_freq_table,
0383     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
0384          TEGRA_PLL_HAS_LOCK_ENABLE,
0385 };
0386 
0387 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
0388     { 12000000,  216000000,  864, 12, 4, 12 },
0389     { 13000000,  216000000,  864, 13, 4, 12 },
0390     { 16800000,  216000000,  720, 14, 4, 12 },
0391     { 19200000,  216000000,  720, 16, 4, 12 },
0392     { 26000000,  216000000,  864, 26, 4, 12 },
0393     { 12000000,  594000000,  594, 12, 1, 12 },
0394     { 13000000,  594000000,  594, 13, 1, 12 },
0395     { 16800000,  594000000,  495, 14, 1, 12 },
0396     { 19200000,  594000000,  495, 16, 1, 12 },
0397     { 26000000,  594000000,  594, 26, 1, 12 },
0398     { 12000000, 1000000000, 1000, 12, 1, 12 },
0399     { 13000000, 1000000000, 1000, 13, 1, 12 },
0400     { 19200000, 1000000000,  625, 12, 1, 12 },
0401     { 26000000, 1000000000, 1000, 26, 1, 12 },
0402     {        0,          0,    0,  0, 0,  0 },
0403 };
0404 
0405 static struct tegra_clk_pll_params pll_d_params = {
0406     .input_min = 2000000,
0407     .input_max = 40000000,
0408     .cf_min = 1000000,
0409     .cf_max = 6000000,
0410     .vco_min = 500000000,
0411     .vco_max = 1000000000,
0412     .base_reg = PLLD_BASE,
0413     .misc_reg = PLLD_MISC,
0414     .lock_mask = PLL_BASE_LOCK,
0415     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0416     .lock_delay = 1000,
0417     .div_nmp = &pllp_nmp,
0418     .freq_table = pll_d_freq_table,
0419     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0420          TEGRA_PLL_HAS_LOCK_ENABLE,
0421 };
0422 
0423 static struct tegra_clk_pll_params pll_d2_params = {
0424     .input_min = 2000000,
0425     .input_max = 40000000,
0426     .cf_min = 1000000,
0427     .cf_max = 6000000,
0428     .vco_min = 500000000,
0429     .vco_max = 1000000000,
0430     .base_reg = PLLD2_BASE,
0431     .misc_reg = PLLD2_MISC,
0432     .lock_mask = PLL_BASE_LOCK,
0433     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0434     .lock_delay = 1000,
0435     .div_nmp = &pllp_nmp,
0436     .freq_table = pll_d_freq_table,
0437     .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0438          TEGRA_PLL_HAS_LOCK_ENABLE,
0439 };
0440 
0441 static const struct pdiv_map pllu_p[] = {
0442     { .pdiv = 1, .hw_val = 1 },
0443     { .pdiv = 2, .hw_val = 0 },
0444     { .pdiv = 0, .hw_val = 0 },
0445 };
0446 
0447 static struct div_nmp pllu_nmp = {
0448     .divm_shift = 0,
0449     .divm_width = 5,
0450     .divn_shift = 8,
0451     .divn_width = 10,
0452     .divp_shift = 20,
0453     .divp_width = 1,
0454 };
0455 
0456 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
0457     { 12000000, 480000000, 960, 12, 2, 12 },
0458     { 13000000, 480000000, 960, 13, 2, 12 },
0459     { 16800000, 480000000, 400,  7, 2,  5 },
0460     { 19200000, 480000000, 200,  4, 2,  3 },
0461     { 26000000, 480000000, 960, 26, 2, 12 },
0462     {        0,         0,   0,  0, 0,  0 },
0463 };
0464 
0465 static struct tegra_clk_pll_params pll_u_params = {
0466     .input_min = 2000000,
0467     .input_max = 40000000,
0468     .cf_min = 1000000,
0469     .cf_max = 6000000,
0470     .vco_min = 480000000,
0471     .vco_max = 960000000,
0472     .base_reg = PLLU_BASE,
0473     .misc_reg = PLLU_MISC,
0474     .lock_mask = PLL_BASE_LOCK,
0475     .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
0476     .lock_delay = 1000,
0477     .pdiv_tohw = pllu_p,
0478     .div_nmp = &pllu_nmp,
0479     .freq_table = pll_u_freq_table,
0480     .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
0481          TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0482 };
0483 
0484 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
0485     /* 1 GHz */
0486     { 12000000, 1000000000, 83, 1, 1, 0 }, /* actual: 996.0 MHz */
0487     { 13000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
0488     { 16800000, 1000000000, 59, 1, 1, 0 }, /* actual: 991.2 MHz */
0489     { 19200000, 1000000000, 52, 1, 1, 0 }, /* actual: 998.4 MHz */
0490     { 26000000, 1000000000, 76, 2, 1, 0 }, /* actual: 988.0 MHz */
0491     {        0,          0,  0, 0, 0, 0 },
0492 };
0493 
0494 static struct tegra_clk_pll_params pll_x_params = {
0495     .input_min = 12000000,
0496     .input_max = 800000000,
0497     .cf_min = 12000000,
0498     .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */
0499     .vco_min = 700000000,
0500     .vco_max = 2400000000U,
0501     .base_reg = PLLX_BASE,
0502     .misc_reg = PLLX_MISC,
0503     .lock_mask = PLL_BASE_LOCK,
0504     .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
0505     .lock_delay = 300,
0506     .iddq_reg = PLLX_MISC3,
0507     .iddq_bit_idx = PLLX_IDDQ_BIT,
0508     .max_p = PLLXC_SW_MAX_P,
0509     .dyn_ramp_reg = PLLX_MISC2,
0510     .stepa_shift = 16,
0511     .stepb_shift = 24,
0512     .pdiv_tohw = pllxc_p,
0513     .div_nmp = &pllxc_nmp,
0514     .freq_table = pll_x_freq_table,
0515     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
0516 };
0517 
0518 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
0519     /* PLLE special case: use cpcon field to store cml divider value */
0520     { 336000000, 100000000, 100, 21, 16, 11 },
0521     { 312000000, 100000000, 200, 26, 24, 13 },
0522     {  12000000, 100000000, 200,  1, 24, 13 },
0523     {         0,         0,   0,  0,  0,  0 },
0524 };
0525 
0526 static const struct pdiv_map plle_p[] = {
0527     { .pdiv =  1, .hw_val =  0 },
0528     { .pdiv =  2, .hw_val =  1 },
0529     { .pdiv =  3, .hw_val =  2 },
0530     { .pdiv =  4, .hw_val =  3 },
0531     { .pdiv =  5, .hw_val =  4 },
0532     { .pdiv =  6, .hw_val =  5 },
0533     { .pdiv =  8, .hw_val =  6 },
0534     { .pdiv = 10, .hw_val =  7 },
0535     { .pdiv = 12, .hw_val =  8 },
0536     { .pdiv = 16, .hw_val =  9 },
0537     { .pdiv = 12, .hw_val = 10 },
0538     { .pdiv = 16, .hw_val = 11 },
0539     { .pdiv = 20, .hw_val = 12 },
0540     { .pdiv = 24, .hw_val = 13 },
0541     { .pdiv = 32, .hw_val = 14 },
0542     { .pdiv =  0, .hw_val =  0 }
0543 };
0544 
0545 static struct div_nmp plle_nmp = {
0546     .divm_shift = 0,
0547     .divm_width = 8,
0548     .divn_shift = 8,
0549     .divn_width = 8,
0550     .divp_shift = 24,
0551     .divp_width = 4,
0552 };
0553 
0554 static struct tegra_clk_pll_params pll_e_params = {
0555     .input_min = 12000000,
0556     .input_max = 1000000000,
0557     .cf_min = 12000000,
0558     .cf_max = 75000000,
0559     .vco_min = 1600000000,
0560     .vco_max = 2400000000U,
0561     .base_reg = PLLE_BASE,
0562     .misc_reg = PLLE_MISC,
0563     .aux_reg = PLLE_AUX,
0564     .lock_mask = PLLE_MISC_LOCK,
0565     .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
0566     .lock_delay = 300,
0567     .pdiv_tohw = plle_p,
0568     .div_nmp = &plle_nmp,
0569     .freq_table = pll_e_freq_table,
0570     .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_LOCK_ENABLE,
0571     .fixed_rate = 100000000,
0572 };
0573 
0574 static struct div_nmp pllre_nmp = {
0575     .divm_shift = 0,
0576     .divm_width = 8,
0577     .divn_shift = 8,
0578     .divn_width = 8,
0579     .divp_shift = 16,
0580     .divp_width = 4,
0581 };
0582 
0583 static struct tegra_clk_pll_params pll_re_vco_params = {
0584     .input_min = 12000000,
0585     .input_max = 1000000000,
0586     .cf_min = 12000000,
0587     .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */
0588     .vco_min = 300000000,
0589     .vco_max = 600000000,
0590     .base_reg = PLLRE_BASE,
0591     .misc_reg = PLLRE_MISC,
0592     .lock_mask = PLLRE_MISC_LOCK,
0593     .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE,
0594     .lock_delay = 300,
0595     .iddq_reg = PLLRE_MISC,
0596     .iddq_bit_idx = PLLRE_IDDQ_BIT,
0597     .div_nmp = &pllre_nmp,
0598     .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE |
0599          TEGRA_PLL_LOCK_MISC,
0600 };
0601 
0602 /* possible OSC frequencies in Hz */
0603 static unsigned long tegra114_input_freq[] = {
0604     [ 0] = 13000000,
0605     [ 1] = 16800000,
0606     [ 4] = 19200000,
0607     [ 5] = 38400000,
0608     [ 8] = 12000000,
0609     [ 9] = 48000000,
0610     [12] = 26000000,
0611 };
0612 
0613 #define MASK(x) (BIT(x) - 1)
0614 
0615 /* peripheral mux definitions */
0616 
0617 static const char *mux_plld_out0_plld2_out0[] = {
0618     "pll_d_out0", "pll_d2_out0",
0619 };
0620 #define mux_plld_out0_plld2_out0_idx NULL
0621 
0622 static const char *mux_pllmcp_clkm[] = {
0623     "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
0624 };
0625 
0626 static const struct clk_div_table pll_re_div_table[] = {
0627     { .val = 0, .div = 1 },
0628     { .val = 1, .div = 2 },
0629     { .val = 2, .div = 3 },
0630     { .val = 3, .div = 4 },
0631     { .val = 4, .div = 5 },
0632     { .val = 5, .div = 6 },
0633     { .val = 0, .div = 0 },
0634 };
0635 
0636 static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
0637     [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
0638     [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
0639     [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
0640     [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
0641     [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
0642     [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
0643     [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
0644     [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
0645     [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
0646     [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
0647     [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
0648     [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
0649     [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
0650     [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
0651     [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
0652     [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
0653     [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
0654     [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
0655     [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
0656     [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
0657     [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
0658     [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
0659     [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
0660     [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
0661     [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
0662     [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
0663     [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
0664     [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
0665     [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
0666     [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
0667     [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
0668     [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
0669     [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
0670     [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
0671     [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
0672     [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
0673     [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
0674     [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
0675     [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
0676     [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
0677     [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
0678     [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
0679     [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
0680     [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
0681     [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
0682     [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
0683     [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
0684     [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
0685     [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
0686     [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
0687     [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
0688     [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
0689     [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
0690     [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
0691     [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
0692     [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
0693     [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
0694     [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
0695     [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
0696     [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
0697     [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
0698     [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
0699     [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
0700     [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
0701     [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
0702     [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
0703     [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
0704     [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
0705     [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
0706     [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
0707     [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
0708     [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
0709     [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
0710     [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
0711     [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
0712     [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
0713     [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
0714     [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
0715     [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
0716     [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
0717     [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
0718     [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
0719     [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
0720     [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
0721     [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
0722     [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
0723     [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
0724     [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
0725     [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
0726     [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
0727     [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
0728     [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
0729     [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
0730     [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
0731     [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
0732     [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
0733     [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
0734     [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
0735     [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
0736     [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
0737     [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
0738     [tegra_clk_osc] = { .dt_id = TEGRA114_CLK_OSC, .present = true },
0739     [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true },
0740     [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true },
0741     [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
0742     [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
0743     [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
0744     [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
0745     [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
0746     [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
0747     [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
0748     [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
0749     [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
0750     [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
0751     [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
0752     [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
0753     [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
0754     [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
0755     [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
0756     [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
0757     [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
0758     [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
0759     [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
0760     [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
0761     [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
0762     [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
0763     [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
0764     [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
0765     [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
0766     [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
0767     [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
0768     [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
0769     [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
0770     [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
0771     [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
0772     [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
0773     [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
0774     [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
0775     [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
0776     [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
0777     [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
0778     [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
0779     [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
0780     [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
0781     [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
0782     [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
0783     [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
0784     [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
0785     [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
0786     [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
0787     [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
0788     [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
0789     [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
0790     [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
0791     [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
0792     [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
0793     [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
0794     [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
0795     [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
0796     [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
0797     [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
0798     [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
0799     [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
0800     [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
0801     [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
0802     [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
0803     [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
0804     [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
0805     [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
0806 };
0807 
0808 static struct tegra_devclk devclks[] __initdata = {
0809     { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
0810     { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
0811     { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K },
0812     { .con_id = "osc", .dt_id = TEGRA114_CLK_OSC },
0813     { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 },
0814     { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 },
0815     { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C },
0816     { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 },
0817     { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 },
0818     { .con_id = "pll_c3", .dt_id = TEGRA114_CLK_PLL_C3 },
0819     { .con_id = "pll_p", .dt_id = TEGRA114_CLK_PLL_P },
0820     { .con_id = "pll_p_out1", .dt_id = TEGRA114_CLK_PLL_P_OUT1 },
0821     { .con_id = "pll_p_out2", .dt_id = TEGRA114_CLK_PLL_P_OUT2 },
0822     { .con_id = "pll_p_out3", .dt_id = TEGRA114_CLK_PLL_P_OUT3 },
0823     { .con_id = "pll_p_out4", .dt_id = TEGRA114_CLK_PLL_P_OUT4 },
0824     { .con_id = "pll_m", .dt_id = TEGRA114_CLK_PLL_M },
0825     { .con_id = "pll_m_out1", .dt_id = TEGRA114_CLK_PLL_M_OUT1 },
0826     { .con_id = "pll_x", .dt_id = TEGRA114_CLK_PLL_X },
0827     { .con_id = "pll_x_out0", .dt_id = TEGRA114_CLK_PLL_X_OUT0 },
0828     { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
0829     { .con_id = "pll_u_480M", .dt_id = TEGRA114_CLK_PLL_U_480M },
0830     { .con_id = "pll_u_60M", .dt_id = TEGRA114_CLK_PLL_U_60M },
0831     { .con_id = "pll_u_48M", .dt_id = TEGRA114_CLK_PLL_U_48M },
0832     { .con_id = "pll_u_12M", .dt_id = TEGRA114_CLK_PLL_U_12M },
0833     { .con_id = "pll_d", .dt_id = TEGRA114_CLK_PLL_D },
0834     { .con_id = "pll_d_out0", .dt_id = TEGRA114_CLK_PLL_D_OUT0 },
0835     { .con_id = "pll_d2", .dt_id = TEGRA114_CLK_PLL_D2 },
0836     { .con_id = "pll_d2_out0", .dt_id = TEGRA114_CLK_PLL_D2_OUT0 },
0837     { .con_id = "pll_a", .dt_id = TEGRA114_CLK_PLL_A },
0838     { .con_id = "pll_a_out0", .dt_id = TEGRA114_CLK_PLL_A_OUT0 },
0839     { .con_id = "pll_re_vco", .dt_id = TEGRA114_CLK_PLL_RE_VCO },
0840     { .con_id = "pll_re_out", .dt_id = TEGRA114_CLK_PLL_RE_OUT },
0841     { .con_id = "pll_e_out0", .dt_id = TEGRA114_CLK_PLL_E_OUT0 },
0842     { .con_id = "spdif_in_sync", .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC },
0843     { .con_id = "i2s0_sync", .dt_id = TEGRA114_CLK_I2S0_SYNC },
0844     { .con_id = "i2s1_sync", .dt_id = TEGRA114_CLK_I2S1_SYNC },
0845     { .con_id = "i2s2_sync", .dt_id = TEGRA114_CLK_I2S2_SYNC },
0846     { .con_id = "i2s3_sync", .dt_id = TEGRA114_CLK_I2S3_SYNC },
0847     { .con_id = "i2s4_sync", .dt_id = TEGRA114_CLK_I2S4_SYNC },
0848     { .con_id = "vimclk_sync", .dt_id = TEGRA114_CLK_VIMCLK_SYNC },
0849     { .con_id = "audio0", .dt_id = TEGRA114_CLK_AUDIO0 },
0850     { .con_id = "audio1", .dt_id = TEGRA114_CLK_AUDIO1 },
0851     { .con_id = "audio2", .dt_id = TEGRA114_CLK_AUDIO2 },
0852     { .con_id = "audio3", .dt_id = TEGRA114_CLK_AUDIO3 },
0853     { .con_id = "audio4", .dt_id = TEGRA114_CLK_AUDIO4 },
0854     { .con_id = "spdif", .dt_id = TEGRA114_CLK_SPDIF },
0855     { .con_id = "audio0_2x", .dt_id = TEGRA114_CLK_AUDIO0_2X },
0856     { .con_id = "audio1_2x", .dt_id = TEGRA114_CLK_AUDIO1_2X },
0857     { .con_id = "audio2_2x", .dt_id = TEGRA114_CLK_AUDIO2_2X },
0858     { .con_id = "audio3_2x", .dt_id = TEGRA114_CLK_AUDIO3_2X },
0859     { .con_id = "audio4_2x", .dt_id = TEGRA114_CLK_AUDIO4_2X },
0860     { .con_id = "spdif_2x", .dt_id = TEGRA114_CLK_SPDIF_2X },
0861     { .con_id = "extern1", .dt_id = TEGRA114_CLK_EXTERN1 },
0862     { .con_id = "extern2", .dt_id = TEGRA114_CLK_EXTERN2 },
0863     { .con_id = "extern3", .dt_id = TEGRA114_CLK_EXTERN3 },
0864     { .con_id = "cclk_g", .dt_id = TEGRA114_CLK_CCLK_G },
0865     { .con_id = "cclk_lp", .dt_id = TEGRA114_CLK_CCLK_LP },
0866     { .con_id = "sclk", .dt_id = TEGRA114_CLK_SCLK },
0867     { .con_id = "hclk", .dt_id = TEGRA114_CLK_HCLK },
0868     { .con_id = "pclk", .dt_id = TEGRA114_CLK_PCLK },
0869     { .con_id = "fuse", .dt_id = TEGRA114_CLK_FUSE },
0870     { .dev_id = "rtc-tegra", .dt_id = TEGRA114_CLK_RTC },
0871     { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
0872 };
0873 
0874 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
0875     "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
0876 };
0877 static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
0878     [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
0879 };
0880 
0881 static struct tegra_audio_clk_info tegra114_audio_plls[] = {
0882     { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
0883 };
0884 
0885 static struct clk **clks;
0886 
0887 static unsigned long osc_freq;
0888 static unsigned long pll_ref_freq;
0889 
0890 static void __init tegra114_fixed_clk_init(void __iomem *clk_base)
0891 {
0892     struct clk *clk;
0893 
0894     /* clk_32k */
0895     clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
0896     clks[TEGRA114_CLK_CLK_32K] = clk;
0897 }
0898 
0899 static void __init tegra114_pll_init(void __iomem *clk_base,
0900                      void __iomem *pmc)
0901 {
0902     struct clk *clk;
0903 
0904     /* PLLC */
0905     clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base,
0906             pmc, 0, &pll_c_params, NULL);
0907     clks[TEGRA114_CLK_PLL_C] = clk;
0908 
0909     /* PLLC_OUT1 */
0910     clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
0911             clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0912             8, 8, 1, NULL);
0913     clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
0914                 clk_base + PLLC_OUT, 1, 0,
0915                 CLK_SET_RATE_PARENT, 0, NULL);
0916     clks[TEGRA114_CLK_PLL_C_OUT1] = clk;
0917 
0918     /* PLLC2 */
0919     clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0,
0920                  &pll_c2_params, NULL);
0921     clks[TEGRA114_CLK_PLL_C2] = clk;
0922 
0923     /* PLLC3 */
0924     clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0,
0925                  &pll_c3_params, NULL);
0926     clks[TEGRA114_CLK_PLL_C3] = clk;
0927 
0928     /* PLLM */
0929     clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc,
0930                  CLK_SET_RATE_GATE, &pll_m_params, NULL);
0931     clks[TEGRA114_CLK_PLL_M] = clk;
0932 
0933     /* PLLM_OUT1 */
0934     clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
0935                 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0936                 8, 8, 1, NULL);
0937     clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
0938                 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
0939                 CLK_SET_RATE_PARENT, 0, NULL);
0940     clks[TEGRA114_CLK_PLL_M_OUT1] = clk;
0941 
0942     /* PLLM_UD */
0943     clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
0944                     CLK_SET_RATE_PARENT, 1, 1);
0945 
0946     /* PLLU */
0947     clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0,
0948                            &pll_u_params, &pll_u_lock);
0949     clks[TEGRA114_CLK_PLL_U] = clk;
0950 
0951     /* PLLU_480M */
0952     clk = clk_register_gate(NULL, "pll_u_480M", "pll_u",
0953                 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE,
0954                 22, 0, &pll_u_lock);
0955     clks[TEGRA114_CLK_PLL_U_480M] = clk;
0956 
0957     /* PLLU_60M */
0958     clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u",
0959                     CLK_SET_RATE_PARENT, 1, 8);
0960     clks[TEGRA114_CLK_PLL_U_60M] = clk;
0961 
0962     /* PLLU_48M */
0963     clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u",
0964                     CLK_SET_RATE_PARENT, 1, 10);
0965     clks[TEGRA114_CLK_PLL_U_48M] = clk;
0966 
0967     /* PLLU_12M */
0968     clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u",
0969                     CLK_SET_RATE_PARENT, 1, 40);
0970     clks[TEGRA114_CLK_PLL_U_12M] = clk;
0971 
0972     /* PLLD */
0973     clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0,
0974                 &pll_d_params, &pll_d_lock);
0975     clks[TEGRA114_CLK_PLL_D] = clk;
0976 
0977     /* PLLD_OUT0 */
0978     clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
0979                     CLK_SET_RATE_PARENT, 1, 2);
0980     clks[TEGRA114_CLK_PLL_D_OUT0] = clk;
0981 
0982     /* PLLD2 */
0983     clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0,
0984                 &pll_d2_params, &pll_d2_lock);
0985     clks[TEGRA114_CLK_PLL_D2] = clk;
0986 
0987     /* PLLD2_OUT0 */
0988     clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
0989                     CLK_SET_RATE_PARENT, 1, 2);
0990     clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
0991 
0992     /* PLLRE */
0993     clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
0994                  0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
0995     clks[TEGRA114_CLK_PLL_RE_VCO] = clk;
0996 
0997     clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0,
0998                      clk_base + PLLRE_BASE, 16, 4, 0,
0999                      pll_re_div_table, &pll_re_lock);
1000     clks[TEGRA114_CLK_PLL_RE_OUT] = clk;
1001 
1002     /* PLLE */
1003     clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref",
1004                       clk_base, 0, &pll_e_params, NULL);
1005     clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1006 }
1007 
1008 #define CLK_SOURCE_VI_SENSOR 0x1a8
1009 
1010 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1011     MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1012 };
1013 
1014 static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1015                         void __iomem *pmc_base)
1016 {
1017     struct clk *clk;
1018     struct tegra_periph_init_data *data;
1019     unsigned int i;
1020 
1021     /* xusb_ss_div2 */
1022     clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
1023                     1, 2);
1024     clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
1025 
1026     /* dsia mux */
1027     clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
1028                    ARRAY_SIZE(mux_plld_out0_plld2_out0),
1029                    CLK_SET_RATE_NO_REPARENT,
1030                    clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
1031     clks[TEGRA114_CLK_DSIA_MUX] = clk;
1032 
1033     /* dsib mux */
1034     clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
1035                    ARRAY_SIZE(mux_plld_out0_plld2_out0),
1036                    CLK_SET_RATE_NO_REPARENT,
1037                    clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
1038     clks[TEGRA114_CLK_DSIB_MUX] = clk;
1039 
1040     clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
1041                          0, 48, periph_clk_enb_refcnt);
1042     clks[TEGRA114_CLK_DSIA] = clk;
1043 
1044     clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
1045                          0, 82, periph_clk_enb_refcnt);
1046     clks[TEGRA114_CLK_DSIB] = clk;
1047 
1048     /* emc mux */
1049     clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1050                    ARRAY_SIZE(mux_pllmcp_clkm),
1051                    CLK_SET_RATE_NO_REPARENT,
1052                    clk_base + CLK_SOURCE_EMC,
1053                    29, 3, 0, &emc_lock);
1054 
1055     clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1056                     &emc_lock);
1057     clks[TEGRA114_CLK_MC] = clk;
1058 
1059     clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base,
1060                          CLK_SET_RATE_PARENT, 56,
1061                          periph_clk_enb_refcnt);
1062     clks[TEGRA114_CLK_MIPI_CAL] = clk;
1063 
1064     for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1065         data = &tegra_periph_clk_list[i];
1066         clk = tegra_clk_register_periph_data(clk_base, data);
1067         clks[data->clk_id] = clk;
1068     }
1069 
1070     tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1071                 &pll_p_params);
1072 }
1073 
1074 /* Tegra114 CPU clock and reset control functions */
1075 static void tegra114_wait_cpu_in_reset(u32 cpu)
1076 {
1077     unsigned int reg;
1078 
1079     do {
1080         reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1081         cpu_relax();
1082     } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
1083 }
1084 
1085 static void tegra114_disable_cpu_clock(u32 cpu)
1086 {
1087     /* flow controller would take care in the power sequence. */
1088 }
1089 
1090 #ifdef CONFIG_PM_SLEEP
1091 static void tegra114_cpu_clock_suspend(void)
1092 {
1093     /* switch coresite to clk_m, save off original source */
1094     tegra114_cpu_clk_sctx.clk_csite_src =
1095                 readl(clk_base + CLK_SOURCE_CSITE);
1096     writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1097 
1098     tegra114_cpu_clk_sctx.cclkg_burst =
1099                 readl(clk_base + CCLKG_BURST_POLICY);
1100     tegra114_cpu_clk_sctx.cclkg_divider =
1101                 readl(clk_base + CCLKG_BURST_POLICY + 4);
1102 }
1103 
1104 static void tegra114_cpu_clock_resume(void)
1105 {
1106     writel(tegra114_cpu_clk_sctx.clk_csite_src,
1107                     clk_base + CLK_SOURCE_CSITE);
1108 
1109     writel(tegra114_cpu_clk_sctx.cclkg_burst,
1110                     clk_base + CCLKG_BURST_POLICY);
1111     writel(tegra114_cpu_clk_sctx.cclkg_divider,
1112                     clk_base + CCLKG_BURST_POLICY + 4);
1113 }
1114 #endif
1115 
1116 static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
1117     .wait_for_reset = tegra114_wait_cpu_in_reset,
1118     .disable_clock  = tegra114_disable_cpu_clock,
1119 #ifdef CONFIG_PM_SLEEP
1120     .suspend    = tegra114_cpu_clock_suspend,
1121     .resume     = tegra114_cpu_clock_resume,
1122 #endif
1123 };
1124 
1125 static const struct of_device_id pmc_match[] __initconst = {
1126     { .compatible = "nvidia,tegra114-pmc" },
1127     { },
1128 };
1129 
1130 /*
1131  * dfll_soc/dfll_ref apparently must be kept enabled, otherwise I2C5
1132  * breaks
1133  */
1134 static struct tegra_clk_init_table init_table[] __initdata = {
1135     { TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
1136     { TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
1137     { TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
1138     { TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
1139     { TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 0 },
1140     { TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 0 },
1141     { TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1142     { TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1143     { TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1144     { TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1145     { TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
1146     { TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
1147     { TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
1148     { TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
1149     { TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
1150     { TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
1151     { TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1152     { TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
1153     { TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1154     { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1155     { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1156     { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1157     { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1158     { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1159     { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1160     { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1161     { TEGRA114_CLK_VDE, TEGRA114_CLK_PLL_P, 408000000, 0 },
1162     { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1163     { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1164     { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1165     { TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1166     { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1167     { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1168     { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1169     /* must be the last entry */
1170     { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1171 };
1172 
1173 static void __init tegra114_clock_apply_init_table(void)
1174 {
1175     tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1176 }
1177 
1178 /**
1179  * tegra114_car_barrier - wait for pending writes to the CAR to complete
1180  *
1181  * Wait for any outstanding writes to the CAR MMIO space from this CPU
1182  * to complete before continuing execution.  No return value.
1183  */
1184 static void tegra114_car_barrier(void)
1185 {
1186     wmb();      /* probably unnecessary */
1187     readl_relaxed(clk_base + CPU_FINETRIM_SELECT);
1188 }
1189 
1190 /**
1191  * tegra114_clock_tune_cpu_trimmers_high - use high-voltage propagation delays
1192  *
1193  * When the CPU rail voltage is in the high-voltage range, use the
1194  * built-in hardwired clock propagation delays in the CPU clock
1195  * shaper.  No return value.
1196  */
1197 void tegra114_clock_tune_cpu_trimmers_high(void)
1198 {
1199     u32 select = 0;
1200 
1201     /* Use hardwired rise->rise & fall->fall clock propagation delays */
1202     select |= ~(CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1203             CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1204             CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1205     writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1206 
1207     tegra114_car_barrier();
1208 }
1209 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_high);
1210 
1211 /**
1212  * tegra114_clock_tune_cpu_trimmers_low - use low-voltage propagation delays
1213  *
1214  * When the CPU rail voltage is in the low-voltage range, use the
1215  * extended clock propagation delays set by
1216  * tegra114_clock_tune_cpu_trimmers_init().  The intention is to
1217  * maintain the input clock duty cycle that the FCPU subsystem
1218  * expects.  No return value.
1219  */
1220 void tegra114_clock_tune_cpu_trimmers_low(void)
1221 {
1222     u32 select = 0;
1223 
1224     /*
1225      * Use software-specified rise->rise & fall->fall clock
1226      * propagation delays (from
1227      * tegra114_clock_tune_cpu_trimmers_init()
1228      */
1229     select |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1230            CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1231            CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1232     writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT);
1233 
1234     tegra114_car_barrier();
1235 }
1236 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_low);
1237 
1238 /**
1239  * tegra114_clock_tune_cpu_trimmers_init - set up and enable clk prop delays
1240  *
1241  * Program extended clock propagation delays into the FCPU clock
1242  * shaper and enable them.  XXX Define the purpose - peak current
1243  * reduction?  No return value.
1244  */
1245 /* XXX Initial voltage rail state assumption issues? */
1246 void tegra114_clock_tune_cpu_trimmers_init(void)
1247 {
1248     u32 dr = 0, r = 0;
1249 
1250     /* Increment the rise->rise clock delay by four steps */
1251     r |= (CPU_FINETRIM_R_FCPU_1_MASK | CPU_FINETRIM_R_FCPU_2_MASK |
1252           CPU_FINETRIM_R_FCPU_3_MASK | CPU_FINETRIM_R_FCPU_4_MASK |
1253           CPU_FINETRIM_R_FCPU_5_MASK | CPU_FINETRIM_R_FCPU_6_MASK);
1254     writel_relaxed(r, clk_base + CPU_FINETRIM_R);
1255 
1256     /*
1257      * Use the rise->rise clock propagation delay specified in the
1258      * r field
1259      */
1260     dr |= (CPU_FINETRIM_1_FCPU_1 | CPU_FINETRIM_1_FCPU_2 |
1261            CPU_FINETRIM_1_FCPU_3 | CPU_FINETRIM_1_FCPU_4 |
1262            CPU_FINETRIM_1_FCPU_5 | CPU_FINETRIM_1_FCPU_6);
1263     writel_relaxed(dr, clk_base + CPU_FINETRIM_DR);
1264 
1265     tegra114_clock_tune_cpu_trimmers_low();
1266 }
1267 EXPORT_SYMBOL(tegra114_clock_tune_cpu_trimmers_init);
1268 
1269 /**
1270  * tegra114_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1271  *
1272  * Assert the reset line of the DFLL's DVCO.  No return value.
1273  */
1274 void tegra114_clock_assert_dfll_dvco_reset(void)
1275 {
1276     u32 v;
1277 
1278     v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1279     v |= (1 << DVFS_DFLL_RESET_SHIFT);
1280     writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1281     tegra114_car_barrier();
1282 }
1283 EXPORT_SYMBOL(tegra114_clock_assert_dfll_dvco_reset);
1284 
1285 /**
1286  * tegra114_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1287  *
1288  * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
1289  * operate.  No return value.
1290  */
1291 void tegra114_clock_deassert_dfll_dvco_reset(void)
1292 {
1293     u32 v;
1294 
1295     v = readl_relaxed(clk_base + RST_DFLL_DVCO);
1296     v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
1297     writel_relaxed(v, clk_base + RST_DFLL_DVCO);
1298     tegra114_car_barrier();
1299 }
1300 EXPORT_SYMBOL(tegra114_clock_deassert_dfll_dvco_reset);
1301 
1302 static void __init tegra114_clock_init(struct device_node *np)
1303 {
1304     struct device_node *node;
1305 
1306     clk_base = of_iomap(np, 0);
1307     if (!clk_base) {
1308         pr_err("ioremap tegra114 CAR failed\n");
1309         return;
1310     }
1311 
1312     node = of_find_matching_node(NULL, pmc_match);
1313     if (!node) {
1314         pr_err("Failed to find pmc node\n");
1315         WARN_ON(1);
1316         return;
1317     }
1318 
1319     pmc_base = of_iomap(node, 0);
1320     if (!pmc_base) {
1321         pr_err("Can't map pmc registers\n");
1322         WARN_ON(1);
1323         return;
1324     }
1325 
1326     clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
1327                 TEGRA114_CLK_PERIPH_BANKS);
1328     if (!clks)
1329         return;
1330 
1331     if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq,
1332                    ARRAY_SIZE(tegra114_input_freq), 1, &osc_freq,
1333                    &pll_ref_freq) < 0)
1334         return;
1335 
1336     tegra114_fixed_clk_init(clk_base);
1337     tegra114_pll_init(clk_base, pmc_base);
1338     tegra114_periph_clk_init(clk_base, pmc_base);
1339     tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1340                  tegra114_audio_plls,
1341                  ARRAY_SIZE(tegra114_audio_plls), 24000000);
1342     tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1343                     &pll_x_params);
1344 
1345     tegra_add_of_provider(np, of_clk_src_onecell_get);
1346     tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1347 
1348     tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1349 
1350     tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1351 }
1352 CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!