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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/io.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/clkdev.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/delay.h>
0012 #include <linux/export.h>
0013 #include <linux/clk/tegra.h>
0014 
0015 #include "clk.h"
0016 #include "clk-id.h"
0017 
0018 #define CLK_SOURCE_I2S0 0x1d8
0019 #define CLK_SOURCE_I2S1 0x100
0020 #define CLK_SOURCE_I2S2 0x104
0021 #define CLK_SOURCE_NDFLASH 0x160
0022 #define CLK_SOURCE_I2S3 0x3bc
0023 #define CLK_SOURCE_I2S4 0x3c0
0024 #define CLK_SOURCE_SPDIF_OUT 0x108
0025 #define CLK_SOURCE_SPDIF_IN 0x10c
0026 #define CLK_SOURCE_PWM 0x110
0027 #define CLK_SOURCE_ADX 0x638
0028 #define CLK_SOURCE_ADX1 0x670
0029 #define CLK_SOURCE_AMX 0x63c
0030 #define CLK_SOURCE_AMX1 0x674
0031 #define CLK_SOURCE_HDA 0x428
0032 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
0033 #define CLK_SOURCE_SBC1 0x134
0034 #define CLK_SOURCE_SBC2 0x118
0035 #define CLK_SOURCE_SBC3 0x11c
0036 #define CLK_SOURCE_SBC4 0x1b4
0037 #define CLK_SOURCE_SBC5 0x3c8
0038 #define CLK_SOURCE_SBC6 0x3cc
0039 #define CLK_SOURCE_SATA_OOB 0x420
0040 #define CLK_SOURCE_SATA 0x424
0041 #define CLK_SOURCE_NDSPEED 0x3f8
0042 #define CLK_SOURCE_VFIR 0x168
0043 #define CLK_SOURCE_SDMMC1 0x150
0044 #define CLK_SOURCE_SDMMC2 0x154
0045 #define CLK_SOURCE_SDMMC3 0x1bc
0046 #define CLK_SOURCE_SDMMC4 0x164
0047 #define CLK_SOURCE_CVE 0x140
0048 #define CLK_SOURCE_TVO 0x188
0049 #define CLK_SOURCE_TVDAC 0x194
0050 #define CLK_SOURCE_VDE 0x1c8
0051 #define CLK_SOURCE_CSITE 0x1d4
0052 #define CLK_SOURCE_LA 0x1f8
0053 #define CLK_SOURCE_TRACE 0x634
0054 #define CLK_SOURCE_OWR 0x1cc
0055 #define CLK_SOURCE_NOR 0x1d0
0056 #define CLK_SOURCE_MIPI 0x174
0057 #define CLK_SOURCE_I2C1 0x124
0058 #define CLK_SOURCE_I2C2 0x198
0059 #define CLK_SOURCE_I2C3 0x1b8
0060 #define CLK_SOURCE_I2C4 0x3c4
0061 #define CLK_SOURCE_I2C5 0x128
0062 #define CLK_SOURCE_I2C6 0x65c
0063 #define CLK_SOURCE_UARTA 0x178
0064 #define CLK_SOURCE_UARTB 0x17c
0065 #define CLK_SOURCE_UARTC 0x1a0
0066 #define CLK_SOURCE_UARTD 0x1c0
0067 #define CLK_SOURCE_UARTE 0x1c4
0068 #define CLK_SOURCE_3D 0x158
0069 #define CLK_SOURCE_2D 0x15c
0070 #define CLK_SOURCE_MPE 0x170
0071 #define CLK_SOURCE_VI_SENSOR 0x1a8
0072 #define CLK_SOURCE_VI 0x148
0073 #define CLK_SOURCE_EPP 0x16c
0074 #define CLK_SOURCE_MSENC 0x1f0
0075 #define CLK_SOURCE_TSEC 0x1f4
0076 #define CLK_SOURCE_HOST1X 0x180
0077 #define CLK_SOURCE_HDMI 0x18c
0078 #define CLK_SOURCE_DISP1 0x138
0079 #define CLK_SOURCE_DISP2 0x13c
0080 #define CLK_SOURCE_CILAB 0x614
0081 #define CLK_SOURCE_CILCD 0x618
0082 #define CLK_SOURCE_CILE 0x61c
0083 #define CLK_SOURCE_DSIALP 0x620
0084 #define CLK_SOURCE_DSIBLP 0x624
0085 #define CLK_SOURCE_TSENSOR 0x3b8
0086 #define CLK_SOURCE_D_AUDIO 0x3d0
0087 #define CLK_SOURCE_DAM0 0x3d8
0088 #define CLK_SOURCE_DAM1 0x3dc
0089 #define CLK_SOURCE_DAM2 0x3e0
0090 #define CLK_SOURCE_ACTMON 0x3e8
0091 #define CLK_SOURCE_EXTERN1 0x3ec
0092 #define CLK_SOURCE_EXTERN2 0x3f0
0093 #define CLK_SOURCE_EXTERN3 0x3f4
0094 #define CLK_SOURCE_I2CSLOW 0x3fc
0095 #define CLK_SOURCE_SE 0x42c
0096 #define CLK_SOURCE_MSELECT 0x3b4
0097 #define CLK_SOURCE_DFLL_REF 0x62c
0098 #define CLK_SOURCE_DFLL_SOC 0x630
0099 #define CLK_SOURCE_SOC_THERM 0x644
0100 #define CLK_SOURCE_XUSB_HOST_SRC 0x600
0101 #define CLK_SOURCE_XUSB_FALCON_SRC 0x604
0102 #define CLK_SOURCE_XUSB_FS_SRC 0x608
0103 #define CLK_SOURCE_XUSB_SS_SRC 0x610
0104 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
0105 #define CLK_SOURCE_ISP 0x144
0106 #define CLK_SOURCE_SOR0 0x414
0107 #define CLK_SOURCE_DPAUX 0x418
0108 #define CLK_SOURCE_ENTROPY 0x628
0109 #define CLK_SOURCE_VI_SENSOR2 0x658
0110 #define CLK_SOURCE_HDMI_AUDIO 0x668
0111 #define CLK_SOURCE_VIC03 0x678
0112 #define CLK_SOURCE_CLK72MHZ 0x66c
0113 #define CLK_SOURCE_DBGAPB 0x718
0114 #define CLK_SOURCE_NVENC 0x6a0
0115 #define CLK_SOURCE_NVDEC 0x698
0116 #define CLK_SOURCE_NVJPG 0x69c
0117 #define CLK_SOURCE_APE 0x6c0
0118 #define CLK_SOURCE_SDMMC_LEGACY 0x694
0119 #define CLK_SOURCE_QSPI 0x6c4
0120 #define CLK_SOURCE_VI_I2C 0x6c8
0121 #define CLK_SOURCE_MIPIBIF 0x660
0122 #define CLK_SOURCE_UARTAPE 0x710
0123 #define CLK_SOURCE_TSECB 0x6d8
0124 #define CLK_SOURCE_MAUD 0x6d4
0125 #define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
0126 #define CLK_SOURCE_DMIC1 0x64c
0127 #define CLK_SOURCE_DMIC2 0x650
0128 #define CLK_SOURCE_DMIC3 0x6bc
0129 
0130 #define MASK(x) (BIT(x) - 1)
0131 
0132 #define MUX(_name, _parents, _offset,   \
0133                 _clk_num, _gate_flags, _clk_id) \
0134     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0135             30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
0136             _clk_num,  _gate_flags, _clk_id, _parents##_idx, 0,\
0137             NULL)
0138 
0139 #define MUX_FLAGS(_name, _parents, _offset,\
0140                 _clk_num, _gate_flags, _clk_id, flags)\
0141     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0142             30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
0143             _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
0144             NULL)
0145 
0146 #define MUX8(_name, _parents, _offset, \
0147                  _clk_num, _gate_flags, _clk_id)    \
0148     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0149             29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
0150             _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
0151             NULL)
0152 
0153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock)  \
0154     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
0155                   29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
0156                   0, TEGRA_PERIPH_NO_GATE, _clk_id,\
0157                   _parents##_idx, 0, _lock)
0158 
0159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id)  \
0160     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
0161                   29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
0162                   0, TEGRA_PERIPH_NO_GATE, _clk_id,\
0163                   _parents##_idx, 0, NULL)
0164 
0165 #define INT(_name, _parents, _offset,   \
0166                 _clk_num, _gate_flags, _clk_id) \
0167     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0168             30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
0169             TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
0170             _clk_id, _parents##_idx, 0, NULL)
0171 
0172 #define INT_FLAGS(_name, _parents, _offset,\
0173                 _clk_num, _gate_flags, _clk_id, flags)\
0174     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0175             30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
0176             TEGRA_DIVIDER_ROUND_UP, _clk_num,  _gate_flags,\
0177             _clk_id, _parents##_idx, flags, NULL)
0178 
0179 #define INT8(_name, _parents, _offset,\
0180                 _clk_num, _gate_flags, _clk_id) \
0181     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0182             29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
0183             TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
0184             _clk_id, _parents##_idx, 0, NULL)
0185 
0186 #define UART(_name, _parents, _offset,\
0187                  _clk_num, _clk_id)         \
0188     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0189             30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
0190             TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
0191             _parents##_idx, 0, NULL)
0192 
0193 #define UART8(_name, _parents, _offset,\
0194                  _clk_num, _clk_id)         \
0195     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0196             29, MASK(3), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \
0197             TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\
0198             _parents##_idx, 0, NULL)
0199 
0200 #define I2C(_name, _parents, _offset,\
0201                  _clk_num, _clk_id)         \
0202     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0203             30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
0204             _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
0205             _parents##_idx, 0, NULL)
0206 
0207 #define XUSB(_name, _parents, _offset, \
0208                  _clk_num, _gate_flags, _clk_id)     \
0209     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
0210             29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \
0211             TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\
0212             _clk_id, _parents##_idx, 0, NULL)
0213 
0214 #define AUDIO(_name, _offset,  _clk_num,\
0215                  _gate_flags, _clk_id)      \
0216     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk,   \
0217             _offset, 16, 0xE01F, 0, 0, 8, 1,        \
0218             TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,  \
0219             _clk_id, mux_d_audio_clk_idx, 0, NULL)
0220 
0221 #define NODIV(_name, _parents, _offset, \
0222                   _mux_shift, _mux_mask, _clk_num, \
0223                   _gate_flags, _clk_id, _lock)      \
0224     TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
0225             _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\
0226             _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\
0227             _clk_id, _parents##_idx, 0, _lock)
0228 
0229 #define GATE(_name, _parent_name,   \
0230                  _clk_num, _gate_flags,  _clk_id, _flags)   \
0231     {                               \
0232         .name = _name,                      \
0233         .clk_id = _clk_id,                  \
0234         .p.parent_name = _parent_name,              \
0235         .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0,     \
0236                 _clk_num, _gate_flags, NULL, NULL), \
0237         .flags = _flags                     \
0238     }
0239 
0240 #define DIV8(_name, _parent_name, _offset, _clk_id, _flags)     \
0241     {                               \
0242         .name = _name,                      \
0243         .clk_id = _clk_id,                  \
0244         .p.parent_name = _parent_name,              \
0245         .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 8, 1,        \
0246                 TEGRA_DIVIDER_ROUND_UP, 0, 0,       \
0247                 NULL, NULL),                \
0248         .offset = _offset,                  \
0249         .flags = _flags,                    \
0250     }
0251 
0252 #define PLLP_BASE 0xa0
0253 #define PLLP_MISC 0xac
0254 #define PLLP_MISC1 0x680
0255 #define PLLP_OUTA 0xa4
0256 #define PLLP_OUTB 0xa8
0257 #define PLLP_OUTC 0x67c
0258 
0259 #define PLL_BASE_LOCK BIT(27)
0260 #define PLL_MISC_LOCK_ENABLE 18
0261 
0262 static DEFINE_SPINLOCK(PLLP_OUTA_lock);
0263 static DEFINE_SPINLOCK(PLLP_OUTB_lock);
0264 static DEFINE_SPINLOCK(PLLP_OUTC_lock);
0265 
0266 #define MUX_I2S_SPDIF(_id)                      \
0267 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
0268                                #_id, "pll_p",\
0269                                "clk_m"};
0270 MUX_I2S_SPDIF(audio0)
0271 MUX_I2S_SPDIF(audio1)
0272 MUX_I2S_SPDIF(audio2)
0273 MUX_I2S_SPDIF(audio3)
0274 MUX_I2S_SPDIF(audio4)
0275 MUX_I2S_SPDIF(audio)
0276 
0277 #define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL
0278 #define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL
0279 #define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL
0280 #define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL
0281 #define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL
0282 #define mux_pllaout0_audio_2x_pllp_clkm_idx NULL
0283 
0284 static const char *mux_pllp_pllc_pllm_clkm[] = {
0285     "pll_p", "pll_c", "pll_m", "clk_m"
0286 };
0287 #define mux_pllp_pllc_pllm_clkm_idx NULL
0288 
0289 static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" };
0290 #define mux_pllp_pllc_pllm_idx NULL
0291 
0292 static const char *mux_pllp_pllc_clk32_clkm[] = {
0293     "pll_p", "pll_c", "clk_32k", "clk_m"
0294 };
0295 #define mux_pllp_pllc_clk32_clkm_idx NULL
0296 
0297 static const char *mux_plla_pllc_pllp_clkm[] = {
0298     "pll_a_out0", "pll_c", "pll_p", "clk_m"
0299 };
0300 #define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx
0301 
0302 static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = {
0303     "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m"
0304 };
0305 static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = {
0306     [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
0307 };
0308 
0309 static const char *mux_pllp_clkm[] = {
0310     "pll_p", "clk_m"
0311 };
0312 static u32 mux_pllp_clkm_idx[] = {
0313     [0] = 0, [1] = 3,
0314 };
0315 
0316 static const char *mux_pllp_clkm_2[] = {
0317     "pll_p", "clk_m"
0318 };
0319 static u32 mux_pllp_clkm_2_idx[] = {
0320     [0] = 2, [1] = 6,
0321 };
0322 
0323 static const char *mux_pllc2_c_c3_pllp_plla1_clkm[] = {
0324     "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a1", "clk_m"
0325 };
0326 static u32 mux_pllc2_c_c3_pllp_plla1_clkm_idx[] = {
0327     [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 6, [5] = 7,
0328 };
0329 
0330 static const char *
0331 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0[] = {
0332     "pll_c4_out1", "pll_c", "pll_c4_out2", "pll_p", "clk_m",
0333     "pll_a_out0", "pll_c4_out0"
0334 };
0335 static u32 mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0_idx[] = {
0336     [0] = 0, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
0337 };
0338 
0339 static const char *mux_pllc_pllp_plla[] = {
0340     "pll_c", "pll_p", "pll_a_out0"
0341 };
0342 static u32 mux_pllc_pllp_plla_idx[] = {
0343     [0] = 1, [1] = 2, [2] = 3,
0344 };
0345 
0346 static const char *mux_clkm_pllc_pllp_plla[] = {
0347     "clk_m", "pll_c", "pll_p", "pll_a_out0"
0348 };
0349 #define mux_clkm_pllc_pllp_plla_idx NULL
0350 
0351 static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm[] = {
0352     "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m"
0353 };
0354 static u32 mux_pllc_pllp_plla1_pllc2_c3_clkm_idx[] = {
0355     [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6,
0356 };
0357 
0358 static const char *mux_pllc2_c_c3_pllp_clkm_plla1_pllc4[] = {
0359     "pll_c2", "pll_c", "pll_c3", "pll_p", "clk_m", "pll_a1", "pll_c4_out0",
0360 };
0361 static u32 mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx[] = {
0362     [0] = 1, [1] = 2, [2] = 3, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
0363 };
0364 
0365 static const char *mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4[] = {
0366     "pll_c", "pll_p", "pll_a1", "pll_c2", "pll_c3", "clk_m", "pll_c4_out0",
0367 };
0368 #define mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4_idx \
0369     mux_pllc2_c_c3_pllp_clkm_plla1_pllc4_idx
0370 
0371 static const char *
0372 mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm[] = {
0373     "pll_a_out0", "pll_c4_out0", "pll_c", "pll_c4_out1", "pll_p",
0374     "pll_c4_out2", "clk_m"
0375 };
0376 #define mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm_idx NULL
0377 
0378 static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
0379     "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
0380 };
0381 #define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx
0382 
0383 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
0384     "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c",
0385     "pll_d2_out0", "clk_m"
0386 };
0387 #define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL
0388 
0389 static const char *mux_pllm_pllc_pllp_plla[] = {
0390     "pll_m", "pll_c", "pll_p", "pll_a_out0"
0391 };
0392 #define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx
0393 
0394 static const char *mux_pllp_pllc_clkm[] = {
0395     "pll_p", "pll_c", "clk_m"
0396 };
0397 static u32 mux_pllp_pllc_clkm_idx[] = {
0398     [0] = 0, [1] = 1, [2] = 3,
0399 };
0400 
0401 static const char *mux_pllp_pllc_clkm_1[] = {
0402     "pll_p", "pll_c", "clk_m"
0403 };
0404 static u32 mux_pllp_pllc_clkm_1_idx[] = {
0405     [0] = 0, [1] = 2, [2] = 5,
0406 };
0407 
0408 static const char *mux_pllp_pllc_plla_clkm[] = {
0409     "pll_p", "pll_c", "pll_a_out0", "clk_m"
0410 };
0411 static u32 mux_pllp_pllc_plla_clkm_idx[] = {
0412     [0] = 0, [1] = 2, [2] = 4, [3] = 6,
0413 };
0414 
0415 static const char *mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2[] = {
0416     "pll_p", "pll_c", "pll_c4_out0", "pll_c4_out1", "clk_m", "pll_c4_out2"
0417 };
0418 static u32 mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2_idx[] = {
0419     [0] = 0, [1] = 2, [2] = 3, [3] = 5, [4] = 6, [5] = 7,
0420 };
0421 
0422 static const char *
0423 mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
0424     "pll_p", "pll_c_out1", "pll_c", "pll_c4_out2", "pll_c4_out1",
0425     "clk_m", "pll_c4_out0"
0426 };
0427 static u32
0428 mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
0429     [0] = 0, [1] = 1, [2] = 2, [3] = 4, [4] = 5, [5] = 6, [6] = 7,
0430 };
0431 
0432 static const char *mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0[] = {
0433     "pll_p", "pll_c4_out2", "pll_c4_out1", "clk_m", "pll_c4_out0"
0434 };
0435 static u32 mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0_idx[] = {
0436     [0] = 0, [1] = 3, [2] = 4, [3] = 6, [4] = 7,
0437 };
0438 
0439 static const char *mux_pllp_pllc2_c_c3_clkm[] = {
0440     "pll_p", "pll_c2", "pll_c", "pll_c3", "clk_m"
0441 };
0442 static u32 mux_pllp_pllc2_c_c3_clkm_idx[] = {
0443     [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 6,
0444 };
0445 
0446 static const char *mux_pllp_clkm_clk32_plle[] = {
0447     "pll_p", "clk_m", "clk_32k", "pll_e"
0448 };
0449 static u32 mux_pllp_clkm_clk32_plle_idx[] = {
0450     [0] = 0, [1] = 2, [2] = 4, [3] = 6,
0451 };
0452 
0453 static const char *mux_pllp_pllp_out3_clkm_clk32k_plla[] = {
0454     "pll_p", "pll_p_out3", "clk_m", "clk_32k", "pll_a_out0"
0455 };
0456 #define mux_pllp_pllp_out3_clkm_clk32k_plla_idx NULL
0457 
0458 static const char *mux_pllp_out3_clkm_pllp_pllc4[] = {
0459     "pll_p_out3", "clk_m", "pll_p", "pll_c4_out0", "pll_c4_out1",
0460     "pll_c4_out2"
0461 };
0462 static u32 mux_pllp_out3_clkm_pllp_pllc4_idx[] = {
0463     [0] = 0, [1] = 3, [2] = 4, [3] = 5, [4] = 6, [5] = 7,
0464 };
0465 
0466 static const char *mux_clkm_pllp_pllre[] = {
0467     "clk_m", "pll_p_out_xusb", "pll_re_out"
0468 };
0469 static u32 mux_clkm_pllp_pllre_idx[] = {
0470     [0] = 0, [1] = 1, [2] = 5,
0471 };
0472 
0473 static const char *mux_pllp_pllc_clkm_clk32[] = {
0474     "pll_p", "pll_c", "clk_m", "clk_32k"
0475 };
0476 #define mux_pllp_pllc_clkm_clk32_idx NULL
0477 
0478 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
0479     "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0"
0480 };
0481 #define mux_plla_clk32_pllp_clkm_plle_idx NULL
0482 
0483 static const char *mux_clkm_pllp_pllc_pllre[] = {
0484     "clk_m", "pll_p", "pll_c", "pll_re_out"
0485 };
0486 static u32 mux_clkm_pllp_pllc_pllre_idx[] = {
0487     [0] = 0, [1] = 1, [2] = 3, [3] = 5,
0488 };
0489 
0490 static const char *mux_clkm_48M_pllp_480M[] = {
0491     "clk_m", "pll_u_48M", "pll_p", "pll_u_480M"
0492 };
0493 static u32 mux_clkm_48M_pllp_480M_idx[] = {
0494     [0] = 0, [1] = 2, [2] = 4, [3] = 6,
0495 };
0496 
0497 static const char *mux_clkm_pllre_clk32_480M[] = {
0498     "clk_m", "pll_re_out", "clk_32k", "pll_u_480M"
0499 };
0500 #define mux_clkm_pllre_clk32_480M_idx NULL
0501 
0502 static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = {
0503     "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
0504 };
0505 static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
0506     [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
0507 };
0508 
0509 static const char *mux_pllp_out3_pllp_pllc_clkm[] = {
0510     "pll_p_out3", "pll_p", "pll_c", "clk_m"
0511 };
0512 static u32 mux_pllp_out3_pllp_pllc_clkm_idx[] = {
0513     [0] = 0, [1] = 1, [2] = 2, [3] = 6,
0514 };
0515 
0516 static const char *mux_ss_div2_60M[] = {
0517     "xusb_ss_div2", "pll_u_60M"
0518 };
0519 #define mux_ss_div2_60M_idx NULL
0520 
0521 static const char *mux_ss_div2_60M_ss[] = {
0522     "xusb_ss_div2", "pll_u_60M", "xusb_ss_src"
0523 };
0524 #define mux_ss_div2_60M_ss_idx NULL
0525 
0526 static const char *mux_ss_clkm[] = {
0527     "xusb_ss_src", "clk_m"
0528 };
0529 #define mux_ss_clkm_idx NULL
0530 
0531 static const char *mux_d_audio_clk[] = {
0532     "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
0533     "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
0534 };
0535 static u32 mux_d_audio_clk_idx[] = {
0536     [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001,
0537     [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007,
0538 };
0539 
0540 static const char *mux_pllp_plld_pllc_clkm[] = {
0541     "pll_p", "pll_d_out0", "pll_c", "clk_m"
0542 };
0543 #define mux_pllp_plld_pllc_clkm_idx NULL
0544 static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = {
0545     "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4",
0546 };
0547 static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = {
0548     [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7,
0549 };
0550 
0551 static const char *mux_pllp_clkm1[] = {
0552     "pll_p", "clk_m",
0553 };
0554 #define mux_pllp_clkm1_idx NULL
0555 
0556 static const char *mux_pllp3_pllc_clkm[] = {
0557     "pll_p_out3", "pll_c", "pll_c2", "clk_m",
0558 };
0559 #define mux_pllp3_pllc_clkm_idx NULL
0560 
0561 static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
0562     "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
0563 };
0564 #define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
0565 
0566 static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
0567     "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
0568 };
0569 static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
0570     [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
0571 };
0572 
0573 /* SOR1 mux'es */
0574 static const char *mux_pllp_plld_plld2_clkm[] = {
0575     "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m"
0576 };
0577 static u32 mux_pllp_plld_plld2_clkm_idx[] = {
0578     [0] = 0, [1] = 2, [2] = 5, [3] = 6
0579 };
0580 
0581 static const char *mux_pllp_pllre_clkm[] = {
0582     "pll_p", "pll_re_out1", "clk_m"
0583 };
0584 
0585 static u32 mux_pllp_pllre_clkm_idx[] = {
0586     [0] = 0, [1] = 2, [2] = 3,
0587 };
0588 
0589 static const char * const mux_dmic1[] = {
0590     "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
0591 };
0592 #define mux_dmic1_idx NULL
0593 
0594 static const char * const mux_dmic2[] = {
0595     "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m"
0596 };
0597 #define mux_dmic2_idx NULL
0598 
0599 static const char * const mux_dmic3[] = {
0600     "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m"
0601 };
0602 #define mux_dmic3_idx NULL
0603 
0604 static struct tegra_periph_init_data periph_clks[] = {
0605     AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
0606     AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
0607     AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1),
0608     AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2),
0609     I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
0610     I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
0611     I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
0612     I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
0613     I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
0614     I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
0615     INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde),
0616     INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi),
0617     INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp),
0618     INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x),
0619     INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe),
0620     INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d),
0621     INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d),
0622     INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8),
0623     INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8),
0624     INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9),
0625     INT8("vi", mux_pllc2_c_c3_pllp_clkm_plla1_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_10),
0626     INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8),
0627     INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc),
0628     INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec),
0629     INT("tsec", mux_pllp_pllc_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec_8),
0630     INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8),
0631     INT8("host1x", mux_pllc4_out1_pllc_pllc4_out2_pllp_clkm_plla_pllc4_out0, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_9),
0632     INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se),
0633     INT8("se", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se_10),
0634     INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8),
0635     INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8),
0636     INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03),
0637     INT8("vic03", mux_pllc_pllp_plla1_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03_8),
0638     INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED),
0639     MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0),
0640     MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1),
0641     MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2),
0642     MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3),
0643     MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4),
0644     MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out),
0645     MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in),
0646     MUX8("spdif_in", mux_pllp_pllc_clkm_1, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in_8),
0647     MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
0648     MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
0649     MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx),
0650     MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda),
0651     MUX("hda", mux_pllp_pllc_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda_8),
0652     MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x),
0653     MUX8("hda2codec_2x", mux_pllp_pllc_plla_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x_8),
0654     MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir),
0655     MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1),
0656     MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2),
0657     MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3),
0658     MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4),
0659     MUX8("sdmmc1", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_9),
0660     MUX8("sdmmc3", mux_pllp_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_9),
0661     MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la),
0662     MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace),
0663     MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr),
0664     MUX("owr", mux_pllp_pllc_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr_8),
0665     MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor),
0666     MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi),
0667     MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor),
0668     MUX("vi_sensor", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_9),
0669     MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab),
0670     MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd),
0671     MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile),
0672     MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp),
0673     MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp),
0674     MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor),
0675     MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon),
0676     MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref),
0677     MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc),
0678     MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow),
0679     MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1),
0680     MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2),
0681     MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3),
0682     MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4),
0683     MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5),
0684     MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6),
0685     MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve),
0686     MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo),
0687     MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac),
0688     MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash),
0689     MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed),
0690     MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob),
0691     MUX("sata_oob", mux_pllp_pllc_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob_8),
0692     MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
0693     MUX("sata", mux_pllp_pllc_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata_8),
0694     MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
0695     MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
0696     MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
0697     MUX("vi_sensor2", mux_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2_8),
0698     MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8),
0699     MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8),
0700     MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8),
0701     MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8),
0702     MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8),
0703     MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8),
0704     MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8),
0705     MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8),
0706     MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8),
0707     MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8),
0708     MUX("sbc1", mux_pllp_pllc_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_9),
0709     MUX("sbc2", mux_pllp_pllc_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_9),
0710     MUX("sbc3", mux_pllp_pllc_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_9),
0711     MUX("sbc4", mux_pllp_pllc_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_9),
0712     MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
0713     MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
0714     MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
0715     MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, TEGRA_PERIPH_NO_RESET, tegra_clk_extern1),
0716     MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, TEGRA_PERIPH_NO_RESET, tegra_clk_extern2),
0717     MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, TEGRA_PERIPH_NO_RESET, tegra_clk_extern3),
0718     MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
0719     MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
0720     MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
0721     MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
0722     MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
0723     MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149,  0, tegra_clk_entropy),
0724     MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149,  0, tegra_clk_entropy_8),
0725     MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
0726     MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz),
0727     MUX8("clk72mhz", mux_pllp_out3_pllp_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz_8),
0728     MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
0729     MUX_FLAGS("csite", mux_pllp_pllre_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite_8, CLK_IGNORE_UNUSED),
0730     NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL),
0731     NODIV("disp1", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1_8, NULL),
0732     NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL),
0733     NODIV("disp2", mux_pllp_plld_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2_8, NULL),
0734     UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta),
0735     UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb),
0736     UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc),
0737     UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd),
0738     UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte),
0739     UART8("uarta", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTA, 6, tegra_clk_uarta_8),
0740     UART8("uartb", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTB, 7, tegra_clk_uartb_8),
0741     UART8("uartc", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTC, 55, tegra_clk_uartc_8),
0742     UART8("uartd", mux_pllp_pllc_pllc4_out0_pllc4_out1_clkm_pllc4_out2, CLK_SOURCE_UARTD, 65, tegra_clk_uartd_8),
0743     XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src),
0744     XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src_8),
0745     XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
0746     XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src_8),
0747     XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
0748     XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
0749     XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src_8),
0750     NODIV("xusb_hs_src", mux_ss_div2_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
0751     NODIV("xusb_hs_src", mux_ss_div2_60M_ss, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(2), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src_4, NULL),
0752     NODIV("xusb_ssp_src", mux_ss_clkm, CLK_SOURCE_XUSB_SS_SRC, 24, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ssp_src, NULL),
0753     XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
0754     XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
0755     MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
0756     MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
0757     MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
0758     MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
0759     MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
0760     MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
0761     MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
0762     I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
0763     MUX("mipibif", mux_pllp_clkm, CLK_SOURCE_MIPIBIF, 173, TEGRA_PERIPH_ON_APB, tegra_clk_mipibif),
0764     MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
0765     MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
0766     MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
0767     MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1),
0768     MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2),
0769     MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3),
0770 };
0771 
0772 static struct tegra_periph_init_data gate_clks[] = {
0773     GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
0774     GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
0775     GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
0776     GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
0777     GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
0778     GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
0779     GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
0780     GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
0781     GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
0782     GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
0783     GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
0784     GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
0785     GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
0786     GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
0787     GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
0788     GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
0789     GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
0790     GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
0791     GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
0792     GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
0793     GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
0794     GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
0795     GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
0796     GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
0797     GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
0798     GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
0799     GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
0800     GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
0801     GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
0802     GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
0803     GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
0804     GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
0805     GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
0806     GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
0807     GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
0808     GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
0809     GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
0810     GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
0811     GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
0812     GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
0813     GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
0814     GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
0815     GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
0816     GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
0817     GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
0818     GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
0819     GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
0820     GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
0821 };
0822 
0823 static struct tegra_periph_init_data div_clks[] = {
0824     DIV8("usb2_hsic_trk", "osc", CLK_SOURCE_USB2_HSIC_TRK, tegra_clk_usb2_hsic_trk, 0),
0825 };
0826 
0827 struct pll_out_data {
0828     char *div_name;
0829     char *pll_out_name;
0830     u32 offset;
0831     int clk_id;
0832     u8 div_shift;
0833     u8 div_flags;
0834     u8 rst_shift;
0835     spinlock_t *lock;
0836 };
0837 
0838 #define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \
0839     {\
0840         .div_name = "pll_p_out" #_num "_div",\
0841         .pll_out_name = "pll_p_out" #_num,\
0842         .offset = _offset,\
0843         .div_shift = _div_shift,\
0844         .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
0845                     TEGRA_DIVIDER_ROUND_UP,\
0846         .rst_shift = _rst_shift,\
0847         .clk_id = tegra_clk_ ## _id,\
0848         .lock = &_offset ##_lock,\
0849     }
0850 
0851 static struct pll_out_data pllp_out_clks[] = {
0852     PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1),
0853     PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2),
0854     PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int),
0855     PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3),
0856     PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4),
0857     PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5),
0858 };
0859 
0860 static void __init periph_clk_init(void __iomem *clk_base,
0861                 struct tegra_clk *tegra_clks)
0862 {
0863     int i;
0864     struct clk *clk;
0865     struct clk **dt_clk;
0866 
0867     for (i = 0; i < ARRAY_SIZE(periph_clks); i++) {
0868         const struct tegra_clk_periph_regs *bank;
0869         struct tegra_periph_init_data *data;
0870 
0871         data = periph_clks + i;
0872 
0873         dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
0874         if (!dt_clk)
0875             continue;
0876 
0877         bank = get_reg_bank(data->periph.gate.clk_num);
0878         if (!bank)
0879             continue;
0880 
0881         data->periph.gate.regs = bank;
0882         clk = tegra_clk_register_periph_data(clk_base, data);
0883         *dt_clk = clk;
0884     }
0885 }
0886 
0887 static void __init gate_clk_init(void __iomem *clk_base,
0888                 struct tegra_clk *tegra_clks)
0889 {
0890     int i;
0891     struct clk *clk;
0892     struct clk **dt_clk;
0893 
0894     for (i = 0; i < ARRAY_SIZE(gate_clks); i++) {
0895         struct tegra_periph_init_data *data;
0896 
0897         data = gate_clks + i;
0898 
0899         dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
0900         if (!dt_clk)
0901             continue;
0902 
0903         clk = tegra_clk_register_periph_gate(data->name,
0904                 data->p.parent_name, data->periph.gate.flags,
0905                 clk_base, data->flags,
0906                 data->periph.gate.clk_num,
0907                 periph_clk_enb_refcnt);
0908         *dt_clk = clk;
0909     }
0910 }
0911 
0912 static void __init div_clk_init(void __iomem *clk_base,
0913                 struct tegra_clk *tegra_clks)
0914 {
0915     int i;
0916     struct clk *clk;
0917     struct clk **dt_clk;
0918 
0919     for (i = 0; i < ARRAY_SIZE(div_clks); i++) {
0920         struct tegra_periph_init_data *data;
0921 
0922         data = div_clks + i;
0923 
0924         dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
0925         if (!dt_clk)
0926             continue;
0927 
0928         clk = tegra_clk_register_divider(data->name,
0929                 data->p.parent_name, clk_base + data->offset,
0930                 data->flags, data->periph.divider.flags,
0931                 data->periph.divider.shift,
0932                 data->periph.divider.width,
0933                 data->periph.divider.frac_width,
0934                 data->periph.divider.lock);
0935         *dt_clk = clk;
0936     }
0937 }
0938 
0939 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base,
0940                 struct tegra_clk *tegra_clks,
0941                 struct tegra_clk_pll_params *pll_params)
0942 {
0943     struct clk *clk;
0944     struct clk **dt_clk;
0945     int i;
0946 
0947     dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks);
0948     if (dt_clk) {
0949         /* PLLP */
0950         clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base,
0951                     pmc_base, 0, pll_params, NULL);
0952         clk_register_clkdev(clk, "pll_p", NULL);
0953         *dt_clk = clk;
0954     }
0955 
0956     for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) {
0957         struct pll_out_data *data;
0958 
0959         data = pllp_out_clks + i;
0960 
0961         dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
0962         if (!dt_clk)
0963             continue;
0964 
0965         clk = tegra_clk_register_divider(data->div_name, "pll_p",
0966                 clk_base + data->offset, 0, data->div_flags,
0967                 data->div_shift, 8, 1, data->lock);
0968         clk = tegra_clk_register_pll_out(data->pll_out_name,
0969                 data->div_name, clk_base + data->offset,
0970                 data->rst_shift + 1, data->rst_shift,
0971                 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,
0972                 data->lock);
0973         *dt_clk = clk;
0974     }
0975 
0976     dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_cpu,
0977             tegra_clks);
0978     if (dt_clk) {
0979         /*
0980          * Tegra210 has control on enabling/disabling PLLP branches to
0981          * CPU, register a gate clock "pll_p_out_cpu" for this gating
0982          * function and parent "pll_p_out4" to it, so when we are
0983          * re-parenting CPU off from "pll_p_out4" the PLLP branching to
0984          * CPU can be disabled automatically.
0985          */
0986         clk = tegra_clk_register_divider("pll_p_out4_div",
0987                 "pll_p_out_cpu", clk_base + PLLP_OUTB, 0, 0, 24,
0988                 8, 1, &PLLP_OUTB_lock);
0989 
0990         dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out4_cpu, tegra_clks);
0991         if (dt_clk) {
0992             clk = tegra_clk_register_pll_out("pll_p_out4",
0993                     "pll_p_out4_div", clk_base + PLLP_OUTB,
0994                     17, 16, CLK_IGNORE_UNUSED |
0995                     CLK_SET_RATE_PARENT, 0,
0996                     &PLLP_OUTB_lock);
0997             *dt_clk = clk;
0998         }
0999     }
1000 
1001     dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_hsio, tegra_clks);
1002     if (dt_clk) {
1003         /* PLLP_OUT_HSIO */
1004         clk = clk_register_gate(NULL, "pll_p_out_hsio", "pll_p",
1005                 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1006                 clk_base + PLLP_MISC1, 29, 0, NULL);
1007         *dt_clk = clk;
1008     }
1009 
1010     dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p_out_xusb, tegra_clks);
1011     if (dt_clk) {
1012         /* PLLP_OUT_XUSB */
1013         clk = clk_register_gate(NULL, "pll_p_out_xusb",
1014                 "pll_p_out_hsio", CLK_SET_RATE_PARENT |
1015                 CLK_IGNORE_UNUSED, clk_base + PLLP_MISC1, 28, 0,
1016                 NULL);
1017         clk_register_clkdev(clk, "pll_p_out_xusb", NULL);
1018         *dt_clk = clk;
1019     }
1020 }
1021 
1022 void __init tegra_periph_clk_init(void __iomem *clk_base,
1023             void __iomem *pmc_base, struct tegra_clk *tegra_clks,
1024             struct tegra_clk_pll_params *pll_params)
1025 {
1026     init_pllp(clk_base, pmc_base, tegra_clks, pll_params);
1027     periph_clk_init(clk_base, tegra_clks);
1028     gate_clk_init(clk_base, tegra_clks);
1029     div_clk_init(clk_base, tegra_clks);
1030 }
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