clk/tegra/clk-tegra-fixed.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #include <linux/io.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/delay.h>
0011 #include <linux/export.h>
0012 #include <linux/clk/tegra.h>
0013
0014 #include "clk.h"
0015 #include "clk-id.h"
0016
0017 #define OSC_CTRL            0x50
0018 #define OSC_CTRL_OSC_FREQ_SHIFT     28
0019 #define OSC_CTRL_PLL_REF_DIV_SHIFT  26
0020 #define OSC_CTRL_MASK           (0x3f2 |    \
0021                     (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
0022
0023 static u32 osc_ctrl_ctx;
0024
0025 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
0026                   unsigned long *input_freqs, unsigned int num,
0027                   unsigned int clk_m_div, unsigned long *osc_freq,
0028                   unsigned long *pll_ref_freq)
0029 {
0030     struct clk *clk, *osc;
0031     struct clk **dt_clk;
0032     u32 val, pll_ref_div;
0033     unsigned osc_idx;
0034
0035     val = readl_relaxed(clk_base + OSC_CTRL);
0036     osc_ctrl_ctx = val & OSC_CTRL_MASK;
0037     osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
0038
0039     if (osc_idx < num)
0040         *osc_freq = input_freqs[osc_idx];
0041     else
0042         *osc_freq = 0;
0043
0044     if (!*osc_freq) {
0045         WARN_ON(1);
0046         return -EINVAL;
0047     }
0048
0049     dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
0050     if (!dt_clk)
0051         return 0;
0052
0053     osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
0054     *dt_clk = osc;
0055
0056     /* osc_div2 */
0057     dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
0058     if (dt_clk) {
0059         clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
0060                         0, 1, 2);
0061         *dt_clk = clk;
0062     }
0063
0064     /* osc_div4 */
0065     dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
0066     if (dt_clk) {
0067         clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
0068                         0, 1, 4);
0069         *dt_clk = clk;
0070     }
0071
0072     dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
0073     if (!dt_clk)
0074         return 0;
0075
0076     clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
0077                     0, 1, clk_m_div);
0078     *dt_clk = clk;
0079
0080     /* pll_ref */
0081     val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
0082     pll_ref_div = 1 << val;
0083     dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
0084     if (!dt_clk)
0085         return 0;
0086
0087     clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
0088                     0, 1, pll_ref_div);
0089     *dt_clk = clk;
0090
0091     if (pll_ref_freq)
0092         *pll_ref_freq = *osc_freq / pll_ref_div;
0093
0094     return 0;
0095 }
0096
0097 void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
0098 {
0099     struct clk *clk;
0100     struct clk **dt_clk;
0101
0102     /* clk_32k */
0103     dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
0104     if (dt_clk) {
0105         clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
0106         *dt_clk = clk;
0107     }
0108 }
0109
0110 void tegra_clk_osc_resume(void __iomem *clk_base)
0111 {
0112     u32 val;
0113
0114     val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
0115     val |= osc_ctrl_ctx;
0116     writel_relaxed(val, clk_base + OSC_CTRL);
0117     fence_udelay(2, clk_base);
0118 }