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0006 #include <linux/io.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/delay.h>
0011 #include <linux/export.h>
0012 #include <linux/clk/tegra.h>
0013
0014 #include "clk.h"
0015 #include "clk-id.h"
0016
0017 #define AUDIO_SYNC_CLK_I2S0 0x4a0
0018 #define AUDIO_SYNC_CLK_I2S1 0x4a4
0019 #define AUDIO_SYNC_CLK_I2S2 0x4a8
0020 #define AUDIO_SYNC_CLK_I2S3 0x4ac
0021 #define AUDIO_SYNC_CLK_I2S4 0x4b0
0022 #define AUDIO_SYNC_CLK_SPDIF 0x4b4
0023 #define AUDIO_SYNC_CLK_DMIC1 0x560
0024 #define AUDIO_SYNC_CLK_DMIC2 0x564
0025 #define AUDIO_SYNC_CLK_DMIC3 0x6b8
0026
0027 #define AUDIO_SYNC_DOUBLER 0x49c
0028
0029 #define PLLA_OUT 0xb4
0030
0031 struct tegra_sync_source_initdata {
0032 char *name;
0033 unsigned long rate;
0034 unsigned long max_rate;
0035 int clk_id;
0036 };
0037
0038 #define SYNC(_name) \
0039 {\
0040 .name = #_name,\
0041 .clk_id = tegra_clk_ ## _name,\
0042 }
0043
0044 struct tegra_audio_clk_initdata {
0045 char *gate_name;
0046 char *mux_name;
0047 u32 offset;
0048 int gate_clk_id;
0049 int mux_clk_id;
0050 };
0051
0052 #define AUDIO(_name, _offset) \
0053 {\
0054 .gate_name = #_name,\
0055 .mux_name = #_name"_mux",\
0056 .offset = _offset,\
0057 .gate_clk_id = tegra_clk_ ## _name,\
0058 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
0059 }
0060
0061 struct tegra_audio2x_clk_initdata {
0062 char *parent;
0063 char *gate_name;
0064 char *name_2x;
0065 char *div_name;
0066 int clk_id;
0067 int clk_num;
0068 u8 div_offset;
0069 };
0070
0071 #define AUDIO2X(_name, _num, _offset) \
0072 {\
0073 .parent = #_name,\
0074 .gate_name = #_name"_2x",\
0075 .name_2x = #_name"_doubler",\
0076 .div_name = #_name"_div",\
0077 .clk_id = tegra_clk_ ## _name ## _2x,\
0078 .clk_num = _num,\
0079 .div_offset = _offset,\
0080 }
0081
0082 static DEFINE_SPINLOCK(clk_doubler_lock);
0083
0084 static const char * const mux_audio_sync_clk[] = { "spdif_in_sync",
0085 "i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync",
0086 "pll_a_out0", "vimclk_sync",
0087 };
0088
0089 static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync",
0090 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
0091 "vimclk_sync",
0092 };
0093
0094 static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
0095 SYNC(spdif_in_sync),
0096 SYNC(i2s0_sync),
0097 SYNC(i2s1_sync),
0098 SYNC(i2s2_sync),
0099 SYNC(i2s3_sync),
0100 SYNC(i2s4_sync),
0101 SYNC(vimclk_sync),
0102 };
0103
0104 static struct tegra_audio_clk_initdata audio_clks[] = {
0105 AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
0106 AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
0107 AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
0108 AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
0109 AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
0110 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
0111 };
0112
0113 static struct tegra_audio_clk_initdata dmic_clks[] = {
0114 AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1),
0115 AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2),
0116 AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3),
0117 };
0118
0119 static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
0120 AUDIO2X(audio0, 113, 24),
0121 AUDIO2X(audio1, 114, 25),
0122 AUDIO2X(audio2, 115, 26),
0123 AUDIO2X(audio3, 116, 27),
0124 AUDIO2X(audio4, 117, 28),
0125 AUDIO2X(spdif, 118, 29),
0126 };
0127
0128 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
0129 struct tegra_clk *tegra_clks,
0130 struct tegra_audio_clk_initdata *sync,
0131 int num_sync_clks,
0132 const char * const *mux_names,
0133 int num_mux_inputs)
0134 {
0135 struct clk *clk;
0136 struct clk **dt_clk;
0137 struct tegra_audio_clk_initdata *data;
0138 int i;
0139
0140 for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
0141 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
0142 if (!dt_clk)
0143 continue;
0144
0145 clk = clk_register_mux(NULL, data->mux_name, mux_names,
0146 num_mux_inputs,
0147 CLK_SET_RATE_NO_REPARENT,
0148 clk_base + data->offset, 0, 3, 0,
0149 NULL);
0150 *dt_clk = clk;
0151
0152 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
0153 if (!dt_clk)
0154 continue;
0155
0156 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
0157 0, clk_base + data->offset, 4,
0158 CLK_GATE_SET_TO_DISABLE, NULL);
0159 *dt_clk = clk;
0160 }
0161 }
0162
0163 void __init tegra_audio_clk_init(void __iomem *clk_base,
0164 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
0165 struct tegra_audio_clk_info *audio_info,
0166 unsigned int num_plls, unsigned long sync_max_rate)
0167 {
0168 struct clk *clk;
0169 struct clk **dt_clk;
0170 int i;
0171
0172 if (!audio_info || num_plls < 1) {
0173 pr_err("No audio data passed to tegra_audio_clk_init\n");
0174 WARN_ON(1);
0175 return;
0176 }
0177
0178 for (i = 0; i < num_plls; i++) {
0179 struct tegra_audio_clk_info *info = &audio_info[i];
0180
0181 dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
0182 if (dt_clk) {
0183 clk = tegra_clk_register_pll(info->name, info->parent,
0184 clk_base, pmc_base, 0, info->pll_params,
0185 NULL);
0186 *dt_clk = clk;
0187 }
0188 }
0189
0190
0191 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
0192 if (dt_clk) {
0193 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
0194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
0195 8, 8, 1, NULL);
0196 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
0197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
0198 CLK_SET_RATE_PARENT, 0, NULL);
0199 *dt_clk = clk;
0200 }
0201
0202 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
0203 struct tegra_sync_source_initdata *data;
0204
0205 data = &sync_source_clks[i];
0206
0207 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
0208 if (!dt_clk)
0209 continue;
0210
0211 clk = tegra_clk_register_sync_source(data->name, sync_max_rate);
0212 *dt_clk = clk;
0213 }
0214
0215 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
0216 ARRAY_SIZE(audio_clks), mux_audio_sync_clk,
0217 ARRAY_SIZE(mux_audio_sync_clk));
0218
0219
0220 for (i = 0; i < ARRAY_SIZE(dmic_clks); i++)
0221 writel_relaxed(1, clk_base + dmic_clks[i].offset);
0222
0223 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks,
0224 ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk,
0225 ARRAY_SIZE(mux_dmic_sync_clk));
0226
0227 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
0228 struct tegra_audio2x_clk_initdata *data;
0229
0230 data = &audio2x_clks[i];
0231 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
0232 if (!dt_clk)
0233 continue;
0234
0235 clk = clk_register_fixed_factor(NULL, data->name_2x,
0236 data->parent, CLK_SET_RATE_PARENT, 2, 1);
0237 clk = tegra_clk_register_divider(data->div_name,
0238 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
0239 0, 0, data->div_offset, 1, 0,
0240 &clk_doubler_lock);
0241 clk = tegra_clk_register_periph_gate(data->gate_name,
0242 data->div_name, TEGRA_PERIPH_NO_RESET,
0243 clk_base, CLK_SET_RATE_PARENT, data->clk_num,
0244 periph_clk_enb_refcnt);
0245 *dt_clk = clk;
0246 }
0247 }
0248
