clk/tegra/clk-sdmmc-mux.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 NVIDIA CORPORATION.  All rights reserved.
0004  *
0005  * based on clk-mux.c
0006  *
0007  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
0008  * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
0009  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
0010  *
0011  */
0012
0013 #include <linux/clk-provider.h>
0014 #include <linux/err.h>
0015 #include <linux/io.h>
0016 #include <linux/types.h>
0017
0018 #include "clk.h"
0019
0020 #define DIV_MASK GENMASK(7, 0)
0021 #define MUX_SHIFT 29
0022 #define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT)
0023 #define SDMMC_MUL 2
0024
0025 #define get_max_div(d) DIV_MASK
0026 #define get_div_field(val) ((val) & DIV_MASK)
0027 #define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT)
0028
0029 static const char * const mux_sdmmc_parents[] = {
0030     "pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m"
0031 };
0032
0033 static const u8 mux_lj_idx[] = {
0034     [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6
0035 };
0036
0037 static const u8 mux_non_lj_idx[] = {
0038     [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6
0039 };
0040
0041 static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw)
0042 {
0043     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0044     int num_parents, i;
0045     u32 src, val;
0046     const u8 *mux_idx;
0047
0048     num_parents = clk_hw_get_num_parents(hw);
0049
0050     val = readl_relaxed(sdmmc_mux->reg);
0051     src = get_mux_field(val);
0052     if (get_div_field(val))
0053         mux_idx = mux_non_lj_idx;
0054     else
0055         mux_idx = mux_lj_idx;
0056
0057     for (i = 0; i < num_parents; i++) {
0058         if (mux_idx[i] == src)
0059             return i;
0060     }
0061
0062     WARN(1, "Unknown parent selector %d\n", src);
0063
0064     return 0;
0065 }
0066
0067 static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index)
0068 {
0069     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0070     u32 val;
0071
0072
0073     val = readl_relaxed(sdmmc_mux->reg);
0074     if (get_div_field(val))
0075         index = mux_non_lj_idx[index];
0076     else
0077         index = mux_lj_idx[index];
0078
0079     val &= ~MUX_MASK;
0080     val |= index << MUX_SHIFT;
0081
0082     writel(val, sdmmc_mux->reg);
0083
0084     return 0;
0085 }
0086
0087 static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw,
0088                            unsigned long parent_rate)
0089 {
0090     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0091     u32 val;
0092     int div;
0093     u64 rate = parent_rate;
0094
0095     val = readl_relaxed(sdmmc_mux->reg);
0096     div = get_div_field(val);
0097
0098     div += SDMMC_MUL;
0099
0100     rate *= SDMMC_MUL;
0101     rate += div - 1;
0102     do_div(rate, div);
0103
0104     return rate;
0105 }
0106
0107 static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw,
0108                     struct clk_rate_request *req)
0109 {
0110     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0111     int div;
0112     unsigned long output_rate = req->best_parent_rate;
0113
0114     req->rate = max(req->rate, req->min_rate);
0115     req->rate = min(req->rate, req->max_rate);
0116
0117     if (!req->rate)
0118         return output_rate;
0119
0120     div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags);
0121     if (div < 0)
0122         div = 0;
0123
0124     if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP)
0125         req->rate =  DIV_ROUND_UP(output_rate * SDMMC_MUL,
0126                       div + SDMMC_MUL);
0127     else
0128         req->rate =  output_rate * SDMMC_MUL / (div + SDMMC_MUL);
0129
0130     return 0;
0131 }
0132
0133 static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate,
0134                   unsigned long parent_rate)
0135 {
0136     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0137     int div;
0138     unsigned long flags = 0;
0139     u32 val;
0140     u8 src;
0141
0142     div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags);
0143     if (div < 0)
0144         return div;
0145
0146     if (sdmmc_mux->lock)
0147         spin_lock_irqsave(sdmmc_mux->lock, flags);
0148
0149     src = clk_sdmmc_mux_get_parent(hw);
0150     if (div)
0151         src = mux_non_lj_idx[src];
0152     else
0153         src = mux_lj_idx[src];
0154
0155     val = src << MUX_SHIFT;
0156     val |= div;
0157     writel(val, sdmmc_mux->reg);
0158     fence_udelay(2, sdmmc_mux->reg);
0159
0160     if (sdmmc_mux->lock)
0161         spin_unlock_irqrestore(sdmmc_mux->lock, flags);
0162
0163     return 0;
0164 }
0165
0166 static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw)
0167 {
0168     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0169     const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
0170     struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
0171
0172     __clk_hw_set_clk(gate_hw, hw);
0173
0174     return gate_ops->is_enabled(gate_hw);
0175 }
0176
0177 static int clk_sdmmc_mux_enable(struct clk_hw *hw)
0178 {
0179     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0180     const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
0181     struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
0182
0183     __clk_hw_set_clk(gate_hw, hw);
0184
0185     return gate_ops->enable(gate_hw);
0186 }
0187
0188 static void clk_sdmmc_mux_disable(struct clk_hw *hw)
0189 {
0190     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0191     const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
0192     struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
0193
0194     gate_ops->disable(gate_hw);
0195 }
0196
0197 static void clk_sdmmc_mux_disable_unused(struct clk_hw *hw)
0198 {
0199     struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw);
0200     const struct clk_ops *gate_ops = sdmmc_mux->gate_ops;
0201     struct clk_hw *gate_hw = &sdmmc_mux->gate.hw;
0202
0203     gate_ops->disable_unused(gate_hw);
0204 }
0205
0206 static void clk_sdmmc_mux_restore_context(struct clk_hw *hw)
0207 {
0208     struct clk_hw *parent = clk_hw_get_parent(hw);
0209     unsigned long parent_rate = clk_hw_get_rate(parent);
0210     unsigned long rate = clk_hw_get_rate(hw);
0211     int parent_id;
0212
0213     parent_id = clk_hw_get_parent_index(hw);
0214     if (WARN_ON(parent_id < 0))
0215         return;
0216
0217     clk_sdmmc_mux_set_parent(hw, parent_id);
0218     clk_sdmmc_mux_set_rate(hw, rate, parent_rate);
0219 }
0220
0221 static const struct clk_ops tegra_clk_sdmmc_mux_ops = {
0222     .get_parent = clk_sdmmc_mux_get_parent,
0223     .set_parent = clk_sdmmc_mux_set_parent,
0224     .determine_rate = clk_sdmmc_mux_determine_rate,
0225     .recalc_rate = clk_sdmmc_mux_recalc_rate,
0226     .set_rate = clk_sdmmc_mux_set_rate,
0227     .is_enabled = clk_sdmmc_mux_is_enabled,
0228     .enable = clk_sdmmc_mux_enable,
0229     .disable = clk_sdmmc_mux_disable,
0230     .disable_unused = clk_sdmmc_mux_disable_unused,
0231     .restore_context = clk_sdmmc_mux_restore_context,
0232 };
0233
0234 struct clk *tegra_clk_register_sdmmc_mux_div(const char *name,
0235     void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags,
0236     unsigned long flags, void *lock)
0237 {
0238     struct clk *clk;
0239     struct clk_init_data init;
0240     const struct tegra_clk_periph_regs *bank;
0241     struct tegra_sdmmc_mux *sdmmc_mux;
0242
0243     init.ops = &tegra_clk_sdmmc_mux_ops;
0244     init.name = name;
0245     init.flags = flags;
0246     init.parent_names = mux_sdmmc_parents;
0247     init.num_parents = ARRAY_SIZE(mux_sdmmc_parents);
0248
0249     bank = get_reg_bank(clk_num);
0250     if (!bank)
0251         return ERR_PTR(-EINVAL);
0252
0253     sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL);
0254     if (!sdmmc_mux)
0255         return ERR_PTR(-ENOMEM);
0256
0257     /* Data in .init is copied by clk_register(), so stack variable OK */
0258     sdmmc_mux->hw.init = &init;
0259     sdmmc_mux->reg = clk_base + offset;
0260     sdmmc_mux->lock = lock;
0261     sdmmc_mux->gate.clk_base = clk_base;
0262     sdmmc_mux->gate.regs = bank;
0263     sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt;
0264     sdmmc_mux->gate.clk_num = clk_num;
0265     sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB;
0266     sdmmc_mux->div_flags = div_flags;
0267     sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops;
0268
0269     clk = clk_register(NULL, &sdmmc_mux->hw);
0270     if (IS_ERR(clk)) {
0271         kfree(sdmmc_mux);
0272         return clk;
0273     }
0274
0275     sdmmc_mux->gate.hw.clk = clk;
0276
0277     return clk;
0278 }