clk/tegra/clk-pll-out.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #include <linux/kernel.h>
0007 #include <linux/io.h>
0008 #include <linux/err.h>
0009 #include <linux/delay.h>
0010 #include <linux/slab.h>
0011 #include <linux/clk-provider.h>
0012
0013 #include "clk.h"
0014
0015 #define pll_out_enb(p) (BIT(p->enb_bit_idx))
0016 #define pll_out_rst(p) (BIT(p->rst_bit_idx))
0017
0018 static int clk_pll_out_is_enabled(struct clk_hw *hw)
0019 {
0020     struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
0021     u32 val = readl_relaxed(pll_out->reg);
0022     int state;
0023
0024     state = (val & pll_out_enb(pll_out)) ? 1 : 0;
0025     if (!(val & (pll_out_rst(pll_out))))
0026         state = 0;
0027     return state;
0028 }
0029
0030 static int clk_pll_out_enable(struct clk_hw *hw)
0031 {
0032     struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
0033     unsigned long flags = 0;
0034     u32 val;
0035
0036     if (pll_out->lock)
0037         spin_lock_irqsave(pll_out->lock, flags);
0038
0039     val = readl_relaxed(pll_out->reg);
0040
0041     val |= (pll_out_enb(pll_out) | pll_out_rst(pll_out));
0042
0043     writel_relaxed(val, pll_out->reg);
0044     udelay(2);
0045
0046     if (pll_out->lock)
0047         spin_unlock_irqrestore(pll_out->lock, flags);
0048
0049     return 0;
0050 }
0051
0052 static void clk_pll_out_disable(struct clk_hw *hw)
0053 {
0054     struct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);
0055     unsigned long flags = 0;
0056     u32 val;
0057
0058     if (pll_out->lock)
0059         spin_lock_irqsave(pll_out->lock, flags);
0060
0061     val = readl_relaxed(pll_out->reg);
0062
0063     val &= ~(pll_out_enb(pll_out) | pll_out_rst(pll_out));
0064
0065     writel_relaxed(val, pll_out->reg);
0066     udelay(2);
0067
0068     if (pll_out->lock)
0069         spin_unlock_irqrestore(pll_out->lock, flags);
0070 }
0071
0072 static void tegra_clk_pll_out_restore_context(struct clk_hw *hw)
0073 {
0074     if (!__clk_get_enable_count(hw->clk))
0075         clk_pll_out_disable(hw);
0076     else
0077         clk_pll_out_enable(hw);
0078 }
0079
0080 const struct clk_ops tegra_clk_pll_out_ops = {
0081     .is_enabled = clk_pll_out_is_enabled,
0082     .enable = clk_pll_out_enable,
0083     .disable = clk_pll_out_disable,
0084     .restore_context = tegra_clk_pll_out_restore_context,
0085 };
0086
0087 struct clk *tegra_clk_register_pll_out(const char *name,
0088         const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
0089         u8 rst_bit_idx, unsigned long flags, u8 pll_out_flags,
0090         spinlock_t *lock)
0091 {
0092     struct tegra_clk_pll_out *pll_out;
0093     struct clk *clk;
0094     struct clk_init_data init;
0095
0096     pll_out = kzalloc(sizeof(*pll_out), GFP_KERNEL);
0097     if (!pll_out)
0098         return ERR_PTR(-ENOMEM);
0099
0100     init.name = name;
0101     init.ops = &tegra_clk_pll_out_ops;
0102     init.parent_names = (parent_name ? &parent_name : NULL);
0103     init.num_parents = (parent_name ? 1 : 0);
0104     init.flags = flags;
0105
0106     pll_out->reg = reg;
0107     pll_out->enb_bit_idx = enb_bit_idx;
0108     pll_out->rst_bit_idx = rst_bit_idx;
0109     pll_out->flags = pll_out_flags;
0110     pll_out->lock = lock;
0111
0112     /* Data in .init is copied by clk_register(), so stack variable OK */
0113     pll_out->hw.init = &init;
0114
0115     clk = clk_register(NULL, &pll_out->hw);
0116     if (IS_ERR(clk))
0117         kfree(pll_out);
0118
0119     return clk;
0120 }