clk/tegra/clk-divider.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #include <linux/kernel.h>
0007 #include <linux/io.h>
0008 #include <linux/err.h>
0009 #include <linux/slab.h>
0010 #include <linux/clk-provider.h>
0011
0012 #include "clk.h"
0013
0014 #define pll_out_override(p) (BIT((p->shift - 6)))
0015 #define div_mask(d) ((1 << (d->width)) - 1)
0016 #define get_mul(d) (1 << d->frac_width)
0017 #define get_max_div(d) div_mask(d)
0018
0019 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
0020
0021 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate,
0022            unsigned long parent_rate)
0023 {
0024     int div;
0025
0026     div = div_frac_get(rate, parent_rate, divider->width,
0027                divider->frac_width, divider->flags);
0028
0029     if (div < 0)
0030         return 0;
0031
0032     return div;
0033 }
0034
0035 static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
0036                          unsigned long parent_rate)
0037 {
0038     struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
0039     u32 reg;
0040     int div, mul;
0041     u64 rate = parent_rate;
0042
0043     reg = readl_relaxed(divider->reg);
0044
0045     if ((divider->flags & TEGRA_DIVIDER_UART) &&
0046         !(reg & PERIPH_CLK_UART_DIV_ENB))
0047         return rate;
0048
0049     div = (reg >> divider->shift) & div_mask(divider);
0050
0051     mul = get_mul(divider);
0052     div += mul;
0053
0054     rate *= mul;
0055     rate += div - 1;
0056     do_div(rate, div);
0057
0058     return rate;
0059 }
0060
0061 static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
0062                    unsigned long *prate)
0063 {
0064     struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
0065     int div, mul;
0066     unsigned long output_rate = *prate;
0067
0068     if (!rate)
0069         return output_rate;
0070
0071     div = get_div(divider, rate, output_rate);
0072     if (div < 0)
0073         return *prate;
0074
0075     mul = get_mul(divider);
0076
0077     return DIV_ROUND_UP(output_rate * mul, div + mul);
0078 }
0079
0080 static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
0081                 unsigned long parent_rate)
0082 {
0083     struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
0084     int div;
0085     unsigned long flags = 0;
0086     u32 val;
0087
0088     div = get_div(divider, rate, parent_rate);
0089     if (div < 0)
0090         return div;
0091
0092     if (divider->lock)
0093         spin_lock_irqsave(divider->lock, flags);
0094
0095     val = readl_relaxed(divider->reg);
0096     val &= ~(div_mask(divider) << divider->shift);
0097     val |= div << divider->shift;
0098
0099     if (divider->flags & TEGRA_DIVIDER_UART) {
0100         if (div)
0101             val |= PERIPH_CLK_UART_DIV_ENB;
0102         else
0103             val &= ~PERIPH_CLK_UART_DIV_ENB;
0104     }
0105
0106     if (divider->flags & TEGRA_DIVIDER_FIXED)
0107         val |= pll_out_override(divider);
0108
0109     writel_relaxed(val, divider->reg);
0110
0111     if (divider->lock)
0112         spin_unlock_irqrestore(divider->lock, flags);
0113
0114     return 0;
0115 }
0116
0117 static void clk_divider_restore_context(struct clk_hw *hw)
0118 {
0119     struct clk_hw *parent = clk_hw_get_parent(hw);
0120     unsigned long parent_rate = clk_hw_get_rate(parent);
0121     unsigned long rate = clk_hw_get_rate(hw);
0122
0123     if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
0124         WARN_ON(1);
0125 }
0126
0127 const struct clk_ops tegra_clk_frac_div_ops = {
0128     .recalc_rate = clk_frac_div_recalc_rate,
0129     .set_rate = clk_frac_div_set_rate,
0130     .round_rate = clk_frac_div_round_rate,
0131     .restore_context = clk_divider_restore_context,
0132 };
0133
0134 struct clk *tegra_clk_register_divider(const char *name,
0135         const char *parent_name, void __iomem *reg,
0136         unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
0137         u8 frac_width, spinlock_t *lock)
0138 {
0139     struct tegra_clk_frac_div *divider;
0140     struct clk *clk;
0141     struct clk_init_data init;
0142
0143     divider = kzalloc(sizeof(*divider), GFP_KERNEL);
0144     if (!divider) {
0145         pr_err("%s: could not allocate fractional divider clk\n",
0146                __func__);
0147         return ERR_PTR(-ENOMEM);
0148     }
0149
0150     init.name = name;
0151     init.ops = &tegra_clk_frac_div_ops;
0152     init.flags = flags;
0153     init.parent_names = parent_name ? &parent_name : NULL;
0154     init.num_parents = parent_name ? 1 : 0;
0155
0156     divider->reg = reg;
0157     divider->shift = shift;
0158     divider->width = width;
0159     divider->frac_width = frac_width;
0160     divider->lock = lock;
0161     divider->flags = clk_divider_flags;
0162
0163     /* Data in .init is copied by clk_register(), so stack variable OK */
0164     divider->hw.init = &init;
0165
0166     clk = clk_register(NULL, &divider->hw);
0167     if (IS_ERR(clk))
0168         kfree(divider);
0169
0170     return clk;
0171 }
0172
0173 static const struct clk_div_table mc_div_table[] = {
0174     { .val = 0, .div = 2 },
0175     { .val = 1, .div = 1 },
0176     { .val = 0, .div = 0 },
0177 };
0178
0179 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
0180                   void __iomem *reg, spinlock_t *lock)
0181 {
0182     return clk_register_divider_table(NULL, name, parent_name,
0183                       CLK_IS_CRITICAL,
0184                       reg, 16, 1, CLK_DIVIDER_READ_ONLY,
0185                       mc_div_table, lock);
0186 }