clk/tegra/clk-dfll.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
0004  * Copyright (C) 2013-2019 NVIDIA Corporation.  All rights reserved.
0005  *
0006  * Aleksandr Frid <afrid@nvidia.com>
0007  * Paul Walmsley <pwalmsley@nvidia.com>
0008  */
0009
0010 #ifndef __DRIVERS_CLK_TEGRA_CLK_DFLL_H
0011 #define __DRIVERS_CLK_TEGRA_CLK_DFLL_H
0012
0013 #include <linux/platform_device.h>
0014 #include <linux/reset.h>
0015 #include <linux/types.h>
0016
0017 #include "cvb.h"
0018
0019 /**
0020  * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
0021  * @dev: struct device * that holds the OPP table for the DFLL
0022  * @max_freq: maximum frequency supported on this SoC
0023  * @cvb: CPU frequency table for this SoC
0024  * @alignment: parameters of the regulator step and offset
0025  * @init_clock_trimmers: callback to initialize clock trimmers
0026  * @set_clock_trimmers_high: callback to tune clock trimmers for high voltage
0027  * @set_clock_trimmers_low: callback to tune clock trimmers for low voltage
0028  */
0029 struct tegra_dfll_soc_data {
0030     struct device *dev;
0031     unsigned long max_freq;
0032     const struct cvb_table *cvb;
0033     struct rail_alignment alignment;
0034
0035     void (*init_clock_trimmers)(void);
0036     void (*set_clock_trimmers_high)(void);
0037     void (*set_clock_trimmers_low)(void);
0038 };
0039
0040 int tegra_dfll_register(struct platform_device *pdev,
0041             struct tegra_dfll_soc_data *soc);
0042 struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
0043 int tegra_dfll_runtime_suspend(struct device *dev);
0044 int tegra_dfll_runtime_resume(struct device *dev);
0045 int tegra_dfll_suspend(struct device *dev);
0046 int tegra_dfll_resume(struct device *dev);
0047
0048 #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */