clk/sunxi/clk-sun8i-mbus.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2014 Chen-Yu Tsai
0004  *
0005  * Chen-Yu Tsai <wens@csie.org>
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/slab.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/of_address.h>
0014
0015 #define SUN8I_MBUS_ENABLE   31
0016 #define SUN8I_MBUS_MUX_SHIFT    24
0017 #define SUN8I_MBUS_MUX_MASK 0x3
0018 #define SUN8I_MBUS_DIV_SHIFT    0
0019 #define SUN8I_MBUS_DIV_WIDTH    3
0020 #define SUN8I_MBUS_MAX_PARENTS  4
0021
0022 static DEFINE_SPINLOCK(sun8i_a23_mbus_lock);
0023
0024 static void __init sun8i_a23_mbus_setup(struct device_node *node)
0025 {
0026     int num_parents = of_clk_get_parent_count(node);
0027     const char **parents;
0028     const char *clk_name = node->name;
0029     struct resource res;
0030     struct clk_divider *div;
0031     struct clk_gate *gate;
0032     struct clk_mux *mux;
0033     struct clk *clk;
0034     void __iomem *reg;
0035     int err;
0036
0037     parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL);
0038     if (!parents)
0039         return;
0040
0041     reg = of_io_request_and_map(node, 0, of_node_full_name(node));
0042     if (IS_ERR(reg)) {
0043         pr_err("Could not get registers for sun8i-mbus-clk\n");
0044         goto err_free_parents;
0045     }
0046
0047     div = kzalloc(sizeof(*div), GFP_KERNEL);
0048     if (!div)
0049         goto err_unmap;
0050
0051     mux = kzalloc(sizeof(*mux), GFP_KERNEL);
0052     if (!mux)
0053         goto err_free_div;
0054
0055     gate = kzalloc(sizeof(*gate), GFP_KERNEL);
0056     if (!gate)
0057         goto err_free_mux;
0058
0059     of_property_read_string(node, "clock-output-names", &clk_name);
0060     of_clk_parent_fill(node, parents, num_parents);
0061
0062     gate->reg = reg;
0063     gate->bit_idx = SUN8I_MBUS_ENABLE;
0064     gate->lock = &sun8i_a23_mbus_lock;
0065
0066     div->reg = reg;
0067     div->shift = SUN8I_MBUS_DIV_SHIFT;
0068     div->width = SUN8I_MBUS_DIV_WIDTH;
0069     div->lock = &sun8i_a23_mbus_lock;
0070
0071     mux->reg = reg;
0072     mux->shift = SUN8I_MBUS_MUX_SHIFT;
0073     mux->mask = SUN8I_MBUS_MUX_MASK;
0074     mux->lock = &sun8i_a23_mbus_lock;
0075
0076     /* The MBUS clocks needs to be always enabled */
0077     clk = clk_register_composite(NULL, clk_name, parents, num_parents,
0078                      &mux->hw, &clk_mux_ops,
0079                      &div->hw, &clk_divider_ops,
0080                      &gate->hw, &clk_gate_ops,
0081                      CLK_IS_CRITICAL);
0082     if (IS_ERR(clk))
0083         goto err_free_gate;
0084
0085     err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
0086     if (err)
0087         goto err_unregister_clk;
0088
0089     kfree(parents); /* parents is deep copied */
0090
0091     return;
0092
0093 err_unregister_clk:
0094     /* TODO: The composite clock stuff will leak a bit here. */
0095     clk_unregister(clk);
0096 err_free_gate:
0097     kfree(gate);
0098 err_free_mux:
0099     kfree(mux);
0100 err_free_div:
0101     kfree(div);
0102 err_unmap:
0103     iounmap(reg);
0104     of_address_to_resource(node, 0, &res);
0105     release_mem_region(res.start, resource_size(&res));
0106 err_free_parents:
0107     kfree(parents);
0108 }
0109 CLK_OF_DECLARE(sun8i_a23_mbus, "allwinner,sun8i-a23-mbus-clk", sun8i_a23_mbus_setup);