clk/sunxi/clk-sun4i-pll3.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2015 Maxime Ripard
0004  *
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/slab.h>
0013 #include <linux/spinlock.h>
0014
0015 #define SUN4I_A10_PLL3_GATE_BIT 31
0016 #define SUN4I_A10_PLL3_DIV_WIDTH    7
0017 #define SUN4I_A10_PLL3_DIV_SHIFT    0
0018
0019 static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
0020
0021 static void __init sun4i_a10_pll3_setup(struct device_node *node)
0022 {
0023     const char *clk_name = node->name, *parent;
0024     struct clk_multiplier *mult;
0025     struct clk_gate *gate;
0026     struct resource res;
0027     void __iomem *reg;
0028     struct clk *clk;
0029     int ret;
0030
0031     of_property_read_string(node, "clock-output-names", &clk_name);
0032     parent = of_clk_get_parent_name(node, 0);
0033
0034     reg = of_io_request_and_map(node, 0, of_node_full_name(node));
0035     if (IS_ERR(reg)) {
0036         pr_err("%s: Could not map the clock registers\n", clk_name);
0037         return;
0038     }
0039
0040     gate = kzalloc(sizeof(*gate), GFP_KERNEL);
0041     if (!gate)
0042         goto err_unmap;
0043
0044     gate->reg = reg;
0045     gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
0046     gate->lock = &sun4i_a10_pll3_lock;
0047
0048     mult = kzalloc(sizeof(*mult), GFP_KERNEL);
0049     if (!mult)
0050         goto err_free_gate;
0051
0052     mult->reg = reg;
0053     mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
0054     mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
0055     mult->lock = &sun4i_a10_pll3_lock;
0056
0057     clk = clk_register_composite(NULL, clk_name,
0058                      &parent, 1,
0059                      NULL, NULL,
0060                      &mult->hw, &clk_multiplier_ops,
0061                      &gate->hw, &clk_gate_ops,
0062                      0);
0063     if (IS_ERR(clk)) {
0064         pr_err("%s: Couldn't register the clock\n", clk_name);
0065         goto err_free_mult;
0066     }
0067
0068     ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
0069     if (ret) {
0070         pr_err("%s: Couldn't register DT provider\n",
0071                clk_name);
0072         goto err_clk_unregister;
0073     }
0074
0075     return;
0076
0077 err_clk_unregister:
0078     clk_unregister_composite(clk);
0079 err_free_mult:
0080     kfree(mult);
0081 err_free_gate:
0082     kfree(gate);
0083 err_unmap:
0084     iounmap(reg);
0085     of_address_to_resource(node, 0, &res);
0086     release_mem_region(res.start, resource_size(&res));
0087 }
0088
0089 CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
0090            sun4i_a10_pll3_setup);