clk/sunxi/clk-factors.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
0004  *
0005  * Adjustable factor-based clock implementation
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/delay.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/of_address.h>
0013 #include <linux/slab.h>
0014 #include <linux/string.h>
0015
0016 #include "clk-factors.h"
0017
0018 /*
0019  * DOC: basic adjustable factor-based clock
0020  *
0021  * Traits of this clock:
0022  * prepare - clk_prepare only ensures that parents are prepared
0023  * enable - clk_enable only ensures that parents are enabled
0024  * rate - rate is adjustable.
0025  *        clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
0026  * parent - fixed parent.  No clk_set_parent support
0027  */
0028
0029 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
0030
0031 #define FACTORS_MAX_PARENTS     5
0032
0033 #define SETMASK(len, pos)       (((1U << (len)) - 1) << (pos))
0034 #define CLRMASK(len, pos)       (~(SETMASK(len, pos)))
0035 #define FACTOR_GET(bit, len, reg)   (((reg) & SETMASK(len, bit)) >> (bit))
0036
0037 #define FACTOR_SET(bit, len, reg, val) \
0038     (((reg) & CLRMASK(len, bit)) | (val << (bit)))
0039
0040 static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
0041                          unsigned long parent_rate)
0042 {
0043     u8 n = 1, k = 0, p = 0, m = 0;
0044     u32 reg;
0045     unsigned long rate;
0046     struct clk_factors *factors = to_clk_factors(hw);
0047     const struct clk_factors_config *config = factors->config;
0048
0049     /* Fetch the register value */
0050     reg = readl(factors->reg);
0051
0052     /* Get each individual factor if applicable */
0053     if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
0054         n = FACTOR_GET(config->nshift, config->nwidth, reg);
0055     if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
0056         k = FACTOR_GET(config->kshift, config->kwidth, reg);
0057     if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
0058         m = FACTOR_GET(config->mshift, config->mwidth, reg);
0059     if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
0060         p = FACTOR_GET(config->pshift, config->pwidth, reg);
0061
0062     if (factors->recalc) {
0063         struct factors_request factors_req = {
0064             .parent_rate = parent_rate,
0065             .n = n,
0066             .k = k,
0067             .m = m,
0068             .p = p,
0069         };
0070
0071         /* get mux details from mux clk structure */
0072         if (factors->mux)
0073             factors_req.parent_index =
0074                 (reg >> factors->mux->shift) &
0075                 factors->mux->mask;
0076
0077         factors->recalc(&factors_req);
0078
0079         return factors_req.rate;
0080     }
0081
0082     /* Calculate the rate */
0083     rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
0084
0085     return rate;
0086 }
0087
0088 static int clk_factors_determine_rate(struct clk_hw *hw,
0089                       struct clk_rate_request *req)
0090 {
0091     struct clk_factors *factors = to_clk_factors(hw);
0092     struct clk_hw *parent, *best_parent = NULL;
0093     int i, num_parents;
0094     unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
0095
0096     /* find the parent that can help provide the fastest rate <= rate */
0097     num_parents = clk_hw_get_num_parents(hw);
0098     for (i = 0; i < num_parents; i++) {
0099         struct factors_request factors_req = {
0100             .rate = req->rate,
0101             .parent_index = i,
0102         };
0103         parent = clk_hw_get_parent_by_index(hw, i);
0104         if (!parent)
0105             continue;
0106         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
0107             parent_rate = clk_hw_round_rate(parent, req->rate);
0108         else
0109             parent_rate = clk_hw_get_rate(parent);
0110
0111         factors_req.parent_rate = parent_rate;
0112         factors->get_factors(&factors_req);
0113         child_rate = factors_req.rate;
0114
0115         if (child_rate <= req->rate && child_rate > best_child_rate) {
0116             best_parent = parent;
0117             best = parent_rate;
0118             best_child_rate = child_rate;
0119         }
0120     }
0121
0122     if (!best_parent)
0123         return -EINVAL;
0124
0125     req->best_parent_hw = best_parent;
0126     req->best_parent_rate = best;
0127     req->rate = best_child_rate;
0128
0129     return 0;
0130 }
0131
0132 static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
0133                 unsigned long parent_rate)
0134 {
0135     struct factors_request req = {
0136         .rate = rate,
0137         .parent_rate = parent_rate,
0138     };
0139     u32 reg;
0140     struct clk_factors *factors = to_clk_factors(hw);
0141     const struct clk_factors_config *config = factors->config;
0142     unsigned long flags = 0;
0143
0144     factors->get_factors(&req);
0145
0146     if (factors->lock)
0147         spin_lock_irqsave(factors->lock, flags);
0148
0149     /* Fetch the register value */
0150     reg = readl(factors->reg);
0151
0152     /* Set up the new factors - macros do not do anything if width is 0 */
0153     reg = FACTOR_SET(config->nshift, config->nwidth, reg, req.n);
0154     reg = FACTOR_SET(config->kshift, config->kwidth, reg, req.k);
0155     reg = FACTOR_SET(config->mshift, config->mwidth, reg, req.m);
0156     reg = FACTOR_SET(config->pshift, config->pwidth, reg, req.p);
0157
0158     /* Apply them now */
0159     writel(reg, factors->reg);
0160
0161     /* delay 500us so pll stabilizes */
0162     __delay((rate >> 20) * 500 / 2);
0163
0164     if (factors->lock)
0165         spin_unlock_irqrestore(factors->lock, flags);
0166
0167     return 0;
0168 }
0169
0170 static const struct clk_ops clk_factors_ops = {
0171     .determine_rate = clk_factors_determine_rate,
0172     .recalc_rate = clk_factors_recalc_rate,
0173     .set_rate = clk_factors_set_rate,
0174 };
0175
0176 static struct clk *__sunxi_factors_register(struct device_node *node,
0177                         const struct factors_data *data,
0178                         spinlock_t *lock, void __iomem *reg,
0179                         unsigned long flags)
0180 {
0181     struct clk *clk;
0182     struct clk_factors *factors;
0183     struct clk_gate *gate = NULL;
0184     struct clk_mux *mux = NULL;
0185     struct clk_hw *gate_hw = NULL;
0186     struct clk_hw *mux_hw = NULL;
0187     const char *clk_name = node->name;
0188     const char *parents[FACTORS_MAX_PARENTS];
0189     int ret, i = 0;
0190
0191     /* if we have a mux, we will have >1 parents */
0192     i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
0193
0194     /*
0195      * some factor clocks, such as pll5 and pll6, may have multiple
0196      * outputs, and have their name designated in factors_data
0197      */
0198     if (data->name)
0199         clk_name = data->name;
0200     else
0201         of_property_read_string(node, "clock-output-names", &clk_name);
0202
0203     factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
0204     if (!factors)
0205         goto err_factors;
0206
0207     /* set up factors properties */
0208     factors->reg = reg;
0209     factors->config = data->table;
0210     factors->get_factors = data->getter;
0211     factors->recalc = data->recalc;
0212     factors->lock = lock;
0213
0214     /* Add a gate if this factor clock can be gated */
0215     if (data->enable) {
0216         gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
0217         if (!gate)
0218             goto err_gate;
0219
0220         factors->gate = gate;
0221
0222         /* set up gate properties */
0223         gate->reg = reg;
0224         gate->bit_idx = data->enable;
0225         gate->lock = factors->lock;
0226         gate_hw = &gate->hw;
0227     }
0228
0229     /* Add a mux if this factor clock can be muxed */
0230     if (data->mux) {
0231         mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
0232         if (!mux)
0233             goto err_mux;
0234
0235         factors->mux = mux;
0236
0237         /* set up gate properties */
0238         mux->reg = reg;
0239         mux->shift = data->mux;
0240         mux->mask = data->muxmask;
0241         mux->lock = factors->lock;
0242         mux_hw = &mux->hw;
0243     }
0244
0245     clk = clk_register_composite(NULL, clk_name,
0246             parents, i,
0247             mux_hw, &clk_mux_ops,
0248             &factors->hw, &clk_factors_ops,
0249             gate_hw, &clk_gate_ops, CLK_IS_CRITICAL);
0250     if (IS_ERR(clk))
0251         goto err_register;
0252
0253     ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
0254     if (ret)
0255         goto err_provider;
0256
0257     return clk;
0258
0259 err_provider:
0260     /* TODO: The composite clock stuff will leak a bit here. */
0261     clk_unregister(clk);
0262 err_register:
0263     kfree(mux);
0264 err_mux:
0265     kfree(gate);
0266 err_gate:
0267     kfree(factors);
0268 err_factors:
0269     return NULL;
0270 }
0271
0272 struct clk *sunxi_factors_register(struct device_node *node,
0273                    const struct factors_data *data,
0274                    spinlock_t *lock,
0275                    void __iomem *reg)
0276 {
0277     return __sunxi_factors_register(node, data, lock, reg, 0);
0278 }
0279
0280 struct clk *sunxi_factors_register_critical(struct device_node *node,
0281                         const struct factors_data *data,
0282                         spinlock_t *lock,
0283                         void __iomem *reg)
0284 {
0285     return __sunxi_factors_register(node, data, lock, reg, CLK_IS_CRITICAL);
0286 }
0287
0288 void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
0289 {
0290     struct clk_hw *hw = __clk_get_hw(clk);
0291     struct clk_factors *factors;
0292
0293     if (!hw)
0294         return;
0295
0296     factors = to_clk_factors(hw);
0297
0298     of_clk_del_provider(node);
0299     /* TODO: The composite clock stuff will leak a bit here. */
0300     clk_unregister(clk);
0301     kfree(factors->mux);
0302     kfree(factors->gate);
0303     kfree(factors);
0304 }