clk/sunxi/clk-a20-gmac.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2013 Emilio López
0004  * Emilio López <emilio@elopez.com.ar>
0005  *
0006  * Copyright 2013 Chen-Yu Tsai
0007  * Chen-Yu Tsai <wens@csie.org>
0008  */
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/slab.h>
0015
0016 static DEFINE_SPINLOCK(gmac_lock);
0017
0018 /**
0019  * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
0020  *
0021  * This clock looks something like this
0022  *                               ________________________
0023  *  MII TX clock from PHY >-----|___________    _________|----> to GMAC core
0024  *  GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
0025  *  Ext. 125MHz RGMII TX clk >--|__divider__/            |
0026  *                              |________________________|
0027  *
0028  * The external 125 MHz reference is optional, i.e. GMAC can use its
0029  * internal TX clock just fine. The A31 GMAC clock module does not have
0030  * the divider controls for the external reference.
0031  *
0032  * To keep it simple, let the GMAC use either the MII TX clock for MII mode,
0033  * and its internal TX clock for GMII and RGMII modes. The GMAC driver should
0034  * select the appropriate source and gate/ungate the output to the PHY.
0035  *
0036  * Only the GMAC should use this clock. Altering the clock so that it doesn't
0037  * match the GMAC's operation parameters will result in the GMAC not being
0038  * able to send traffic out. The GMAC driver should set the clock rate and
0039  * enable/disable this clock to configure the required state. The clock
0040  * driver then responds by auto-reparenting the clock.
0041  */
0042
0043 #define SUN7I_A20_GMAC_GPIT 2
0044 #define SUN7I_A20_GMAC_MASK 0x3
0045 #define SUN7I_A20_GMAC_PARENTS  2
0046
0047 static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
0048     0x00, /* Select mii_phy_tx_clk */
0049     0x02, /* Select gmac_int_tx_clk */
0050 };
0051
0052 static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
0053 {
0054     struct clk *clk;
0055     struct clk_mux *mux;
0056     struct clk_gate *gate;
0057     const char *clk_name = node->name;
0058     const char *parents[SUN7I_A20_GMAC_PARENTS];
0059     void __iomem *reg;
0060
0061     if (of_property_read_string(node, "clock-output-names", &clk_name))
0062         return;
0063
0064     /* allocate mux and gate clock structs */
0065     mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
0066     if (!mux)
0067         return;
0068
0069     gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
0070     if (!gate)
0071         goto free_mux;
0072
0073     /* gmac clock requires exactly 2 parents */
0074     if (of_clk_parent_fill(node, parents, 2) != 2)
0075         goto free_gate;
0076
0077     reg = of_iomap(node, 0);
0078     if (!reg)
0079         goto free_gate;
0080
0081     /* set up gate and fixed rate properties */
0082     gate->reg = reg;
0083     gate->bit_idx = SUN7I_A20_GMAC_GPIT;
0084     gate->lock = &gmac_lock;
0085     mux->reg = reg;
0086     mux->mask = SUN7I_A20_GMAC_MASK;
0087     mux->table = sun7i_a20_gmac_mux_table;
0088     mux->lock = &gmac_lock;
0089
0090     clk = clk_register_composite(NULL, clk_name,
0091             parents, SUN7I_A20_GMAC_PARENTS,
0092             &mux->hw, &clk_mux_ops,
0093             NULL, NULL,
0094             &gate->hw, &clk_gate_ops,
0095             0);
0096
0097     if (IS_ERR(clk))
0098         goto iounmap_reg;
0099
0100     of_clk_add_provider(node, of_clk_src_simple_get, clk);
0101
0102     return;
0103
0104 iounmap_reg:
0105     iounmap(reg);
0106 free_gate:
0107     kfree(gate);
0108 free_mux:
0109     kfree(mux);
0110 }
0111 CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
0112         sun7i_a20_gmac_clk_setup);