clk/sunxi/clk-a10-pll2.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2013 Emilio López
0004  * Emilio López <emilio@elopez.com.ar>
0005  *
0006  * Copyright 2015 Maxime Ripard
0007  * Maxime Ripard <maxime.ripard@free-electrons.com>
0008  */
0009
0010 #include <linux/clk-provider.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/slab.h>
0015
0016 #include <dt-bindings/clock/sun4i-a10-pll2.h>
0017
0018 #define SUN4I_PLL2_ENABLE       31
0019
0020 #define SUN4I_PLL2_PRE_DIV_SHIFT    0
0021 #define SUN4I_PLL2_PRE_DIV_WIDTH    5
0022 #define SUN4I_PLL2_PRE_DIV_MASK     GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
0023
0024 #define SUN4I_PLL2_N_SHIFT      8
0025 #define SUN4I_PLL2_N_WIDTH      7
0026 #define SUN4I_PLL2_N_MASK       GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
0027
0028 #define SUN4I_PLL2_POST_DIV_SHIFT   26
0029 #define SUN4I_PLL2_POST_DIV_WIDTH   4
0030 #define SUN4I_PLL2_POST_DIV_MASK    GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
0031
0032 #define SUN4I_PLL2_POST_DIV_VALUE   4
0033
0034 #define SUN4I_PLL2_OUTPUTS      4
0035
0036 static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
0037
0038 static void __init sun4i_pll2_setup(struct device_node *node,
0039                     int post_div_offset)
0040 {
0041     const char *clk_name = node->name, *parent;
0042     struct clk **clks, *base_clk, *prediv_clk;
0043     struct clk_onecell_data *clk_data;
0044     struct clk_multiplier *mult;
0045     struct clk_gate *gate;
0046     void __iomem *reg;
0047     u32 val;
0048
0049     reg = of_io_request_and_map(node, 0, of_node_full_name(node));
0050     if (IS_ERR(reg))
0051         return;
0052
0053     clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
0054     if (!clk_data)
0055         goto err_unmap;
0056
0057     clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
0058     if (!clks)
0059         goto err_free_data;
0060
0061     parent = of_clk_get_parent_name(node, 0);
0062     prediv_clk = clk_register_divider(NULL, "pll2-prediv",
0063                       parent, 0, reg,
0064                       SUN4I_PLL2_PRE_DIV_SHIFT,
0065                       SUN4I_PLL2_PRE_DIV_WIDTH,
0066                       CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
0067                       &sun4i_a10_pll2_lock);
0068     if (IS_ERR(prediv_clk)) {
0069         pr_err("Couldn't register the prediv clock\n");
0070         goto err_free_array;
0071     }
0072
0073     /* Setup the gate part of the PLL2 */
0074     gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
0075     if (!gate)
0076         goto err_unregister_prediv;
0077
0078     gate->reg = reg;
0079     gate->bit_idx = SUN4I_PLL2_ENABLE;
0080     gate->lock = &sun4i_a10_pll2_lock;
0081
0082     /* Setup the multiplier part of the PLL2 */
0083     mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
0084     if (!mult)
0085         goto err_free_gate;
0086
0087     mult->reg = reg;
0088     mult->shift = SUN4I_PLL2_N_SHIFT;
0089     mult->width = 7;
0090     mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
0091             CLK_MULTIPLIER_ROUND_CLOSEST;
0092     mult->lock = &sun4i_a10_pll2_lock;
0093
0094     parent = __clk_get_name(prediv_clk);
0095     base_clk = clk_register_composite(NULL, "pll2-base",
0096                       &parent, 1,
0097                       NULL, NULL,
0098                       &mult->hw, &clk_multiplier_ops,
0099                       &gate->hw, &clk_gate_ops,
0100                       CLK_SET_RATE_PARENT);
0101     if (IS_ERR(base_clk)) {
0102         pr_err("Couldn't register the base multiplier clock\n");
0103         goto err_free_multiplier;
0104     }
0105
0106     parent = __clk_get_name(base_clk);
0107
0108     /*
0109      * PLL2-1x
0110      *
0111      * This is supposed to have a post divider, but we won't need
0112      * to use it, we just need to initialise it to 4, and use a
0113      * fixed divider.
0114      */
0115     val = readl(reg);
0116     val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
0117     val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
0118     writel(val, reg);
0119
0120     of_property_read_string_index(node, "clock-output-names",
0121                       SUN4I_A10_PLL2_1X, &clk_name);
0122     clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
0123                                 parent,
0124                                 CLK_SET_RATE_PARENT,
0125                                 1,
0126                                 SUN4I_PLL2_POST_DIV_VALUE);
0127     WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
0128
0129     /*
0130      * PLL2-2x
0131      *
0132      * This clock doesn't use the post divider, and really is just
0133      * a fixed divider from the PLL2 base clock.
0134      */
0135     of_property_read_string_index(node, "clock-output-names",
0136                       SUN4I_A10_PLL2_2X, &clk_name);
0137     clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
0138                                 parent,
0139                                 CLK_SET_RATE_PARENT,
0140                                 1, 2);
0141     WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
0142
0143     /* PLL2-4x */
0144     of_property_read_string_index(node, "clock-output-names",
0145                       SUN4I_A10_PLL2_4X, &clk_name);
0146     clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
0147                                 parent,
0148                                 CLK_SET_RATE_PARENT,
0149                                 1, 1);
0150     WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
0151
0152     /* PLL2-8x */
0153     of_property_read_string_index(node, "clock-output-names",
0154                       SUN4I_A10_PLL2_8X, &clk_name);
0155     clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
0156                                 parent,
0157                                 CLK_SET_RATE_PARENT,
0158                                 2, 1);
0159     WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
0160
0161     clk_data->clks = clks;
0162     clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
0163     of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
0164
0165     return;
0166
0167 err_free_multiplier:
0168     kfree(mult);
0169 err_free_gate:
0170     kfree(gate);
0171 err_unregister_prediv:
0172     clk_unregister_divider(prediv_clk);
0173 err_free_array:
0174     kfree(clks);
0175 err_free_data:
0176     kfree(clk_data);
0177 err_unmap:
0178     iounmap(reg);
0179 }
0180
0181 static void __init sun4i_a10_pll2_setup(struct device_node *node)
0182 {
0183     sun4i_pll2_setup(node, 0);
0184 }
0185
0186 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
0187            sun4i_a10_pll2_setup);
0188
0189 static void __init sun5i_a13_pll2_setup(struct device_node *node)
0190 {
0191     sun4i_pll2_setup(node, 1);
0192 }
0193
0194 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
0195            sun5i_a13_pll2_setup);