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0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/slab.h>
0013
0014 static DEFINE_SPINLOCK(mod1_lock);
0015
0016 #define SUN4I_MOD1_ENABLE 31
0017 #define SUN4I_MOD1_MUX 16
0018 #define SUN4I_MOD1_MUX_WIDTH 2
0019 #define SUN4I_MOD1_MAX_PARENTS 4
0020
0021 static void __init sun4i_mod1_clk_setup(struct device_node *node)
0022 {
0023 struct clk *clk;
0024 struct clk_mux *mux;
0025 struct clk_gate *gate;
0026 const char *parents[4];
0027 const char *clk_name = node->name;
0028 void __iomem *reg;
0029 int i;
0030
0031 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
0032 if (IS_ERR(reg))
0033 return;
0034
0035 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
0036 if (!mux)
0037 goto err_unmap;
0038
0039 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
0040 if (!gate)
0041 goto err_free_mux;
0042
0043 of_property_read_string(node, "clock-output-names", &clk_name);
0044 i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
0045
0046 gate->reg = reg;
0047 gate->bit_idx = SUN4I_MOD1_ENABLE;
0048 gate->lock = &mod1_lock;
0049 mux->reg = reg;
0050 mux->shift = SUN4I_MOD1_MUX;
0051 mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
0052 mux->lock = &mod1_lock;
0053
0054 clk = clk_register_composite(NULL, clk_name, parents, i,
0055 &mux->hw, &clk_mux_ops,
0056 NULL, NULL,
0057 &gate->hw, &clk_gate_ops, CLK_SET_RATE_PARENT);
0058 if (IS_ERR(clk))
0059 goto err_free_gate;
0060
0061 of_clk_add_provider(node, of_clk_src_simple_get, clk);
0062
0063 return;
0064
0065 err_free_gate:
0066 kfree(gate);
0067 err_free_mux:
0068 kfree(mux);
0069 err_unmap:
0070 iounmap(reg);
0071 }
0072 CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk",
0073 sun4i_mod1_clk_setup);