clk/sunxi-ng/ccu_nm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
0004  */
0005
0006 #ifndef _CCU_NM_H_
0007 #define _CCU_NM_H_
0008
0009 #include <linux/clk-provider.h>
0010
0011 #include "ccu_common.h"
0012 #include "ccu_div.h"
0013 #include "ccu_frac.h"
0014 #include "ccu_mult.h"
0015 #include "ccu_sdm.h"
0016
0017 /*
0018  * struct ccu_nm - Definition of an N-M clock
0019  *
0020  * Clocks based on the formula parent * N / M
0021  */
0022 struct ccu_nm {
0023     u32         enable;
0024     u32         lock;
0025
0026     struct ccu_mult_internal    n;
0027     struct ccu_div_internal     m;
0028     struct ccu_frac_internal    frac;
0029     struct ccu_sdm_internal     sdm;
0030
0031     unsigned int        fixed_post_div;
0032     unsigned int        min_rate;
0033     unsigned int        max_rate;
0034
0035     struct ccu_common   common;
0036 };
0037
0038 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg,  \
0039                     _nshift, _nwidth,       \
0040                     _mshift, _mwidth,       \
0041                     _sdm_table, _sdm_en,        \
0042                     _sdm_reg, _sdm_reg_en,      \
0043                     _gate, _lock, _flags)       \
0044     struct ccu_nm _struct = {                   \
0045         .enable     = _gate,                \
0046         .lock       = _lock,                \
0047         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0048         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0049         .sdm        = _SUNXI_CCU_SDM(_sdm_table, _sdm_en,   \
0050                          _sdm_reg, _sdm_reg_en),\
0051         .common     = {                 \
0052             .reg        = _reg,             \
0053             .features   = CCU_FEATURE_SIGMA_DELTA_MOD,  \
0054             .hw.init    = CLK_HW_INIT(_name,        \
0055                               _parent,      \
0056                               &ccu_nm_ops,  \
0057                               _flags),      \
0058         },                          \
0059     }
0060
0061 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
0062                      _nshift, _nwidth,      \
0063                      _mshift, _mwidth,      \
0064                      _frac_en, _frac_sel,       \
0065                      _frac_rate_0, _frac_rate_1,    \
0066                      _gate, _lock, _flags)      \
0067     struct ccu_nm _struct = {                   \
0068         .enable     = _gate,                \
0069         .lock       = _lock,                \
0070         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0071         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0072         .frac       = _SUNXI_CCU_FRAC(_frac_en, _frac_sel,  \
0073                           _frac_rate_0,     \
0074                           _frac_rate_1),    \
0075         .common     = {                 \
0076             .reg        = _reg,             \
0077             .features   = CCU_FEATURE_FRACTIONAL,   \
0078             .hw.init    = CLK_HW_INIT(_name,        \
0079                               _parent,      \
0080                               &ccu_nm_ops,  \
0081                               _flags),      \
0082         },                          \
0083     }
0084
0085 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent,   \
0086                          _reg, _min_rate,       \
0087                          _nshift, _nwidth,      \
0088                          _mshift, _mwidth,      \
0089                          _frac_en, _frac_sel,   \
0090                          _frac_rate_0, _frac_rate_1,\
0091                          _gate, _lock, _flags)  \
0092     struct ccu_nm _struct = {                   \
0093         .enable     = _gate,                \
0094         .lock       = _lock,                \
0095         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0096         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0097         .frac       = _SUNXI_CCU_FRAC(_frac_en, _frac_sel,  \
0098                           _frac_rate_0,     \
0099                           _frac_rate_1),    \
0100         .min_rate   = _min_rate,                \
0101         .common     = {                 \
0102             .reg        = _reg,             \
0103             .features   = CCU_FEATURE_FRACTIONAL,   \
0104             .hw.init    = CLK_HW_INIT(_name,        \
0105                               _parent,      \
0106                               &ccu_nm_ops,  \
0107                               _flags),      \
0108         },                          \
0109     }
0110
0111 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name,    \
0112                          _parent, _reg,     \
0113                          _min_rate, _max_rate,  \
0114                          _nshift, _nwidth,  \
0115                          _mshift, _mwidth,  \
0116                          _frac_en, _frac_sel,   \
0117                          _frac_rate_0,      \
0118                          _frac_rate_1,      \
0119                          _gate, _lock, _flags)  \
0120     struct ccu_nm _struct = {                   \
0121         .enable     = _gate,                \
0122         .lock       = _lock,                \
0123         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0124         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0125         .frac       = _SUNXI_CCU_FRAC(_frac_en, _frac_sel,  \
0126                           _frac_rate_0,     \
0127                           _frac_rate_1),    \
0128         .min_rate   = _min_rate,                \
0129         .max_rate   = _max_rate,                \
0130         .common     = {                 \
0131             .reg        = _reg,             \
0132             .features   = CCU_FEATURE_FRACTIONAL,   \
0133             .hw.init    = CLK_HW_INIT(_name,        \
0134                               _parent,      \
0135                               &ccu_nm_ops,  \
0136                               _flags),      \
0137         },                          \
0138     }
0139
0140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,  \
0141                     _nshift, _nwidth,           \
0142                     _mshift, _mwidth,           \
0143                     _gate, _lock, _flags)       \
0144     struct ccu_nm _struct = {                   \
0145         .enable     = _gate,                \
0146         .lock       = _lock,                \
0147         .n      = _SUNXI_CCU_MULT(_nshift, _nwidth),    \
0148         .m      = _SUNXI_CCU_DIV(_mshift, _mwidth), \
0149         .common     = {                 \
0150             .reg        = _reg,             \
0151             .hw.init    = CLK_HW_INIT(_name,        \
0152                               _parent,      \
0153                               &ccu_nm_ops,  \
0154                               _flags),      \
0155         },                          \
0156     }
0157
0158 static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw)
0159 {
0160     struct ccu_common *common = hw_to_ccu_common(hw);
0161
0162     return container_of(common, struct ccu_nm, common);
0163 }
0164
0165 extern const struct clk_ops ccu_nm_ops;
0166
0167 #endif /* _CCU_NM_H_ */